[arm64] Assembler support for internal references.

src/arm64/instructions-arm64.h

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef V8_ARM64_INSTRUCTIONS_ARM64_H_
 #define V8_ARM64_INSTRUCTIONS_ARM64_H_
 
 #include "src/arm64/constants-arm64.h"
 #include "src/arm64/utils-arm64.h"
 #include "src/globals.h"
@@ skipping 103 matching lines @@
 
   int32_t SignedBits(int msb, int lsb) const {
     int32_t bits = *(reinterpret_cast<const int32_t*>(this));
     return signed_bitextract_32(msb, lsb, bits);
   }
 
   Instr Mask(uint32_t mask) const {
     return InstructionBits() & mask;
   }
 
+  V8_INLINE const Instruction* following(int count = 1) const {
+    return InstructionAtOffset(count * static_cast<int>(kInstructionSize));
+  }
+
   V8_INLINE Instruction* following(int count = 1) {
     return InstructionAtOffset(count * static_cast<int>(kInstructionSize));
   }
 
+  V8_INLINE const Instruction* preceding(int count = 1) const {
+    return following(-count);
+  }
+
   V8_INLINE Instruction* preceding(int count = 1) {
     return following(-count);
   }
 
   #define DEFINE_GETTER(Name, HighBit, LowBit, Func)             \
   int64_t Name() const { return Func(HighBit, LowBit); }
   INSTRUCTION_FIELDS_LIST(DEFINE_GETTER)
   #undef DEFINE_GETTER
 
   // ImmPCRel is a compound field (not present in INSTRUCTION_FIELDS_LIST),
@@ skipping 44 matching lines @@
   }
 
   bool IsPCRelAddressing() const {
     return Mask(PCRelAddressingFMask) == PCRelAddressingFixed;
   }
 
   bool IsAdr() const {
     return Mask(PCRelAddressingMask) == ADR;
   }
 
+  bool IsBrk() const { return Mask(ExceptionMask) == BRK; }
+
+  bool IsUnresolvedInternalReference() const {
+    // Unresolved internal references are encoded as two consecutive brk
+    // instructions.
+    return IsBrk() && following()->IsBrk();
+  }
+
   bool IsLogicalImmediate() const {
     return Mask(LogicalImmediateFMask) == LogicalImmediateFixed;
   }
 
   bool IsAddSubImmediate() const {
     return Mask(AddSubImmediateFMask) == AddSubImmediateFixed;
   }
 
   bool IsAddSubShifted() const {
     return Mask(AddSubShiftedFMask) == AddSubShiftedFixed;
@@ skipping 97 matching lines @@
     switch (BranchType()) {
       case CondBranchType: return ImmCondBranch();
       case UncondBranchType: return ImmUncondBranch();
       case CompareBranchType: return ImmCmpBranch();
       case TestBranchType: return ImmTestBranch();
       default: UNREACHABLE();
     }
     return 0;
   }
 
+  int ImmUnresolvedInternalReference() const {
+    DCHECK(IsUnresolvedInternalReference());
+    // Unresolved references are encoded as two consecutive brk instructions.
+    // The associated immediate is made of the two 16-bit payloads.
+    int32_t high16 = ImmException();
+    int32_t low16 = following()->ImmException();
+    return (high16 << 16) | low16;
+  }
+
   bool IsBranchAndLinkToRegister() const {
     return Mask(UnconditionalBranchToRegisterMask) == BLR;
   }
 
   bool IsMovz() const {
     return (Mask(MoveWideImmediateMask) == MOVZ_x) ||
            (Mask(MoveWideImmediateMask) == MOVZ_w);
   }
 
   bool IsMovk() const {
@@ skipping 23 matching lines @@
 
   // Find the target of this instruction. 'this' may be a branch or a
   // PC-relative addressing instruction.
   Instruction* ImmPCOffsetTarget();
 
   static bool IsValidImmPCOffset(ImmBranchType branch_type, int32_t offset);
   bool IsTargetInImmPCOffsetRange(Instruction* target);
   // Patch a PC-relative offset to refer to 'target'. 'this' may be a branch or
   // a PC-relative addressing instruction.
   void SetImmPCOffsetTarget(Instruction* target);
+  void SetUnresolvedInternalReferenceImmTarget(Instruction* target);
   // Patch a literal load instruction to load from 'source'.
   void SetImmLLiteral(Instruction* source);
 
   uintptr_t LiteralAddress() {
     int offset = ImmLLiteral() << kLoadLiteralScaleLog2;
     return reinterpret_cast<uintptr_t>(this) + offset;
   }
 
   enum CheckAlignment { NO_CHECK, CHECK_ALIGNMENT };
 
+  V8_INLINE const Instruction* InstructionAtOffset(
+      int64_t offset, CheckAlignment check = CHECK_ALIGNMENT) const {
+    // The FUZZ_disasm test relies on no check being done.
+    DCHECK(check == NO_CHECK || IsAligned(offset, kInstructionSize));
+    return this + offset;
+  }
+
   V8_INLINE Instruction* InstructionAtOffset(
-      int64_t offset,
-      CheckAlignment check = CHECK_ALIGNMENT) {
-    Address addr = reinterpret_cast<Address>(this) + offset;
+      int64_t offset, CheckAlignment check = CHECK_ALIGNMENT) {
     // The FUZZ_disasm test relies on no check being done.
-    DCHECK(check == NO_CHECK || IsAddressAligned(addr, kInstructionSize));
-    return Cast(addr);
+    DCHECK(check == NO_CHECK || IsAligned(offset, kInstructionSize));
+    return this + offset;
   }
 
   template<typename T> V8_INLINE static Instruction* Cast(T src) {
     return reinterpret_cast<Instruction*>(src);
   }
 
   V8_INLINE ptrdiff_t DistanceTo(Instruction* target) {
     return reinterpret_cast<Address>(target) - reinterpret_cast<Address>(this);
   }
 
@@ skipping 121 matching lines @@
   TRACE_ENABLE   = 1 << 6,
   TRACE_DISABLE  = 2 << 6,
   TRACE_OVERRIDE = 3 << 6
 };
 
 
 } }  // namespace v8::internal
 
 
 #endif  // V8_ARM64_INSTRUCTIONS_ARM64_H_