| Index: src/compiler/arm64/instruction-selector-arm64.cc
|
| diff --git a/src/compiler/arm64/instruction-selector-arm64.cc b/src/compiler/arm64/instruction-selector-arm64.cc
|
| index 7f8e9ea3bdd5d17522e0e72c1cf68ac468629053..fedda248d8272e43da6037ae772471d5b34e851f 100644
|
| --- a/src/compiler/arm64/instruction-selector-arm64.cc
|
| +++ b/src/compiler/arm64/instruction-selector-arm64.cc
|
| @@ -1606,20 +1606,35 @@ void InstructionSelector::VisitFloat64ExtractHighWord32(Node* node) {
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|
|
|
|
| void InstructionSelector::VisitFloat64InsertLowWord32(Node* node) {
|
| - // TODO(arm64): Some AArch64 specialist should be able to improve this.
|
| Arm64OperandGenerator g(this);
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| Node* left = node->InputAt(0);
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| Node* right = node->InputAt(1);
|
| + if (left->opcode() == IrOpcode::kFloat64InsertHighWord32 &&
|
| + CanCover(node, left)) {
|
| + Node* right_of_left = left->InputAt(1);
|
| + Emit(kArm64Bfi, g.DefineSameAsFirst(right), g.UseRegister(right),
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| + g.UseRegister(right_of_left), g.TempImmediate(32),
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| + g.TempImmediate(32));
|
| + Emit(kArm64Float64MoveU64, g.DefineAsRegister(node), g.UseRegister(right));
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| + return;
|
| + }
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| Emit(kArm64Float64InsertLowWord32, g.DefineAsRegister(node),
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| g.UseRegister(left), g.UseRegister(right));
|
| }
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|
|
|
|
| void InstructionSelector::VisitFloat64InsertHighWord32(Node* node) {
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| - // TODO(arm64): Some AArch64 specialist should be able to improve this.
|
| Arm64OperandGenerator g(this);
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| Node* left = node->InputAt(0);
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| Node* right = node->InputAt(1);
|
| + if (left->opcode() == IrOpcode::kFloat64InsertLowWord32 &&
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| + CanCover(node, left)) {
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| + Node* right_of_left = left->InputAt(1);
|
| + Emit(kArm64Bfi, g.DefineSameAsFirst(left), g.UseRegister(right_of_left),
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| + g.UseRegister(right), g.TempImmediate(32), g.TempImmediate(32));
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| + Emit(kArm64Float64MoveU64, g.DefineAsRegister(node), g.UseRegister(left));
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| + return;
|
| + }
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| Emit(kArm64Float64InsertHighWord32, g.DefineAsRegister(node),
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| g.UseRegister(left), g.UseRegister(right));
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| }
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|
|