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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ | 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ | 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
7 | 7 |
8 namespace v8 { | 8 namespace v8 { |
9 namespace internal { | 9 namespace internal { |
10 namespace compiler { | 10 namespace compiler { |
11 | 11 |
12 // MIPS64-specific opcodes that specify which assembly sequence to emit. | 12 // MIPS64-specific opcodes that specify which assembly sequence to emit. |
13 // Most opcodes specify a single instruction. | 13 // Most opcodes specify a single instruction. |
14 #define TARGET_ARCH_OPCODE_LIST(V) \ | 14 #define TARGET_ARCH_OPCODE_LIST(V) \ |
15 V(Mips64Add) \ | 15 V(Mips64Add) \ |
16 V(Mips64Dadd) \ | 16 V(Mips64Dadd) \ |
17 V(Mips64Sub) \ | 17 V(Mips64Sub) \ |
18 V(Mips64Dsub) \ | 18 V(Mips64Dsub) \ |
19 V(Mips64Mul) \ | 19 V(Mips64Mul) \ |
20 V(Mips64MulHigh) \ | 20 V(Mips64MulHigh) \ |
21 V(Mips64MulHighU) \ | 21 V(Mips64MulHighU) \ |
22 V(Mips64Dmul) \ | 22 V(Mips64Dmul) \ |
23 V(Mips64Div) \ | 23 V(Mips64Div) \ |
24 V(Mips64Ddiv) \ | 24 V(Mips64Ddiv) \ |
25 V(Mips64DivU) \ | 25 V(Mips64DivU) \ |
26 V(Mips64DdivU) \ | 26 V(Mips64DdivU) \ |
27 V(Mips64Mod) \ | 27 V(Mips64Mod) \ |
28 V(Mips64Dmod) \ | 28 V(Mips64Dmod) \ |
29 V(Mips64ModU) \ | 29 V(Mips64ModU) \ |
30 V(Mips64DmodU) \ | 30 V(Mips64DmodU) \ |
31 V(Mips64And) \ | 31 V(Mips64And) \ |
32 V(Mips64Or) \ | 32 V(Mips64Or) \ |
33 V(Mips64Xor) \ | 33 V(Mips64Xor) \ |
34 V(Mips64Shl) \ | 34 V(Mips64Shl) \ |
35 V(Mips64Shr) \ | 35 V(Mips64Shr) \ |
36 V(Mips64Sar) \ | 36 V(Mips64Sar) \ |
37 V(Mips64Ext) \ | 37 V(Mips64Ext) \ |
38 V(Mips64Dext) \ | 38 V(Mips64Dext) \ |
39 V(Mips64Dshl) \ | 39 V(Mips64Dshl) \ |
40 V(Mips64Dshr) \ | 40 V(Mips64Dshr) \ |
41 V(Mips64Dsar) \ | 41 V(Mips64Dsar) \ |
42 V(Mips64Ror) \ | 42 V(Mips64Ror) \ |
43 V(Mips64Dror) \ | 43 V(Mips64Dror) \ |
44 V(Mips64Mov) \ | 44 V(Mips64Mov) \ |
45 V(Mips64Tst) \ | 45 V(Mips64Tst) \ |
46 V(Mips64Tst32) \ | 46 V(Mips64Tst32) \ |
47 V(Mips64Cmp) \ | 47 V(Mips64Cmp) \ |
48 V(Mips64Cmp32) \ | 48 V(Mips64Cmp32) \ |
49 V(Mips64CmpD) \ | 49 V(Mips64CmpD) \ |
50 V(Mips64AddD) \ | 50 V(Mips64AddD) \ |
51 V(Mips64SubD) \ | 51 V(Mips64SubD) \ |
52 V(Mips64MulD) \ | 52 V(Mips64MulD) \ |
53 V(Mips64DivD) \ | 53 V(Mips64DivD) \ |
54 V(Mips64ModD) \ | 54 V(Mips64ModD) \ |
55 V(Mips64SqrtD) \ | 55 V(Mips64SqrtD) \ |
56 V(Mips64Float64RoundDown) \ | 56 V(Mips64Float64RoundDown) \ |
57 V(Mips64Float64RoundTruncate) \ | 57 V(Mips64Float64RoundTruncate) \ |
58 V(Mips64Float64RoundUp) \ | 58 V(Mips64Float64RoundUp) \ |
59 V(Mips64CvtSD) \ | 59 V(Mips64CvtSD) \ |
60 V(Mips64CvtDS) \ | 60 V(Mips64CvtDS) \ |
61 V(Mips64TruncWD) \ | 61 V(Mips64TruncWD) \ |
62 V(Mips64TruncUwD) \ | 62 V(Mips64TruncUwD) \ |
63 V(Mips64CvtDW) \ | 63 V(Mips64CvtDW) \ |
64 V(Mips64CvtDUw) \ | 64 V(Mips64CvtDUw) \ |
65 V(Mips64Lb) \ | 65 V(Mips64Lb) \ |
66 V(Mips64Lbu) \ | 66 V(Mips64Lbu) \ |
67 V(Mips64Sb) \ | 67 V(Mips64Sb) \ |
68 V(Mips64Lh) \ | 68 V(Mips64Lh) \ |
69 V(Mips64Lhu) \ | 69 V(Mips64Lhu) \ |
70 V(Mips64Sh) \ | 70 V(Mips64Sh) \ |
71 V(Mips64Ld) \ | 71 V(Mips64Ld) \ |
72 V(Mips64Lw) \ | 72 V(Mips64Lw) \ |
73 V(Mips64Sw) \ | 73 V(Mips64Sw) \ |
74 V(Mips64Sd) \ | 74 V(Mips64Sd) \ |
75 V(Mips64Lwc1) \ | 75 V(Mips64Lwc1) \ |
76 V(Mips64Swc1) \ | 76 V(Mips64Swc1) \ |
77 V(Mips64Ldc1) \ | 77 V(Mips64Ldc1) \ |
78 V(Mips64Sdc1) \ | 78 V(Mips64Sdc1) \ |
79 V(Mips64FmoveLowUwD) \ | 79 V(Mips64Float64ExtractLowWord32) \ |
80 V(Mips64FmoveLowDUw) \ | 80 V(Mips64Float64ExtractHighWord32) \ |
81 V(Mips64FmoveHighUwD) \ | 81 V(Mips64Float64InsertLowWord32) \ |
82 V(Mips64FmoveHighDUw) \ | 82 V(Mips64Float64InsertHighWord32) \ |
83 V(Mips64Push) \ | 83 V(Mips64Push) \ |
84 V(Mips64StoreToStackSlot) \ | 84 V(Mips64StoreToStackSlot) \ |
85 V(Mips64StackClaim) \ | 85 V(Mips64StackClaim) \ |
86 V(Mips64StoreWriteBarrier) | 86 V(Mips64StoreWriteBarrier) |
87 | 87 |
88 | 88 |
89 // Addressing modes represent the "shape" of inputs to an instruction. | 89 // Addressing modes represent the "shape" of inputs to an instruction. |
90 // Many instructions support multiple addressing modes. Addressing modes | 90 // Many instructions support multiple addressing modes. Addressing modes |
91 // are encoded into the InstructionCode of the instruction and tell the | 91 // are encoded into the InstructionCode of the instruction and tell the |
92 // code generator after register allocation which assembler method to call. | 92 // code generator after register allocation which assembler method to call. |
93 // | 93 // |
94 // We use the following local notation for addressing modes: | 94 // We use the following local notation for addressing modes: |
95 // | 95 // |
96 // R = register | 96 // R = register |
97 // O = register or stack slot | 97 // O = register or stack slot |
98 // D = double register | 98 // D = double register |
99 // I = immediate (handle, external, int32) | 99 // I = immediate (handle, external, int32) |
100 // MRI = [register + immediate] | 100 // MRI = [register + immediate] |
101 // MRR = [register + register] | 101 // MRR = [register + register] |
102 // TODO(plind): Add the new r6 address modes. | 102 // TODO(plind): Add the new r6 address modes. |
103 #define TARGET_ADDRESSING_MODE_LIST(V) \ | 103 #define TARGET_ADDRESSING_MODE_LIST(V) \ |
104 V(MRI) /* [%r0 + K] */ \ | 104 V(MRI) /* [%r0 + K] */ \ |
105 V(MRR) /* [%r0 + %r1] */ | 105 V(MRR) /* [%r0 + %r1] */ |
106 | 106 |
107 | 107 |
108 } // namespace compiler | 108 } // namespace compiler |
109 } // namespace internal | 109 } // namespace internal |
110 } // namespace v8 | 110 } // namespace v8 |
111 | 111 |
112 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ | 112 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
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