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Side by Side Diff: src/compiler/mips/instruction-codes-mips.h

Issue 1006523002: MIPS: Improve naming of turbofan ops for %_DoubleHi, %_DoubleLo and %_ConstructDouble. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 5 years, 9 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 43 matching lines...) Expand 10 before | Expand all | Expand 10 after
54 V(MipsSb) \ 54 V(MipsSb) \
55 V(MipsLh) \ 55 V(MipsLh) \
56 V(MipsLhu) \ 56 V(MipsLhu) \
57 V(MipsSh) \ 57 V(MipsSh) \
58 V(MipsLw) \ 58 V(MipsLw) \
59 V(MipsSw) \ 59 V(MipsSw) \
60 V(MipsLwc1) \ 60 V(MipsLwc1) \
61 V(MipsSwc1) \ 61 V(MipsSwc1) \
62 V(MipsLdc1) \ 62 V(MipsLdc1) \
63 V(MipsSdc1) \ 63 V(MipsSdc1) \
64 V(MipsFmoveLowUwD) \ 64 V(MipsFloat64ExtractLowWord32) \
65 V(MipsFmoveLowDUw) \ 65 V(MipsFloat64ExtractHighWord32) \
66 V(MipsFmoveHighUwD) \ 66 V(MipsFloat64InsertLowWord32) \
67 V(MipsFmoveHighDUw) \ 67 V(MipsFloat64InsertHighWord32) \
68 V(MipsPush) \ 68 V(MipsPush) \
69 V(MipsStoreToStackSlot) \ 69 V(MipsStoreToStackSlot) \
70 V(MipsStackClaim) \ 70 V(MipsStackClaim) \
71 V(MipsStoreWriteBarrier) 71 V(MipsStoreWriteBarrier)
72 72
73 73
74 // Addressing modes represent the "shape" of inputs to an instruction. 74 // Addressing modes represent the "shape" of inputs to an instruction.
75 // Many instructions support multiple addressing modes. Addressing modes 75 // Many instructions support multiple addressing modes. Addressing modes
76 // are encoded into the InstructionCode of the instruction and tell the 76 // are encoded into the InstructionCode of the instruction and tell the
77 // code generator after register allocation which assembler method to call. 77 // code generator after register allocation which assembler method to call.
(...skipping 10 matching lines...) Expand all
88 #define TARGET_ADDRESSING_MODE_LIST(V) \ 88 #define TARGET_ADDRESSING_MODE_LIST(V) \
89 V(MRI) /* [%r0 + K] */ \ 89 V(MRI) /* [%r0 + K] */ \
90 V(MRR) /* [%r0 + %r1] */ 90 V(MRR) /* [%r0 + %r1] */
91 91
92 92
93 } // namespace compiler 93 } // namespace compiler
94 } // namespace internal 94 } // namespace internal
95 } // namespace v8 95 } // namespace v8
96 96
97 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 97 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
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