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1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include <limits.h> | 5 #include <limits.h> |
6 #include <stdarg.h> | 6 #include <stdarg.h> |
7 #include <stdlib.h> | 7 #include <stdlib.h> |
8 #include <cmath> | 8 #include <cmath> |
9 | 9 |
10 #include "src/v8.h" | 10 #include "src/v8.h" |
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1988 case COP1X: | 1988 case COP1X: |
1989 break; | 1989 break; |
1990 case SPECIAL: | 1990 case SPECIAL: |
1991 switch (instr->FunctionFieldRaw()) { | 1991 switch (instr->FunctionFieldRaw()) { |
1992 case JR: | 1992 case JR: |
1993 case JALR: | 1993 case JALR: |
1994 *next_pc = get_register(instr->RsValue()); | 1994 *next_pc = get_register(instr->RsValue()); |
1995 *return_addr_reg = instr->RdValue(); | 1995 *return_addr_reg = instr->RdValue(); |
1996 break; | 1996 break; |
1997 case SLL: | 1997 case SLL: |
1998 *alu_out = (int32_t)rt << sa; | 1998 *alu_out = static_cast<int32_t>(rt) << sa; |
1999 break; | 1999 break; |
2000 case DSLL: | 2000 case DSLL: |
2001 *alu_out = rt << sa; | 2001 *alu_out = rt << sa; |
2002 break; | 2002 break; |
2003 case DSLL32: | 2003 case DSLL32: |
2004 *alu_out = rt << sa << 32; | 2004 *alu_out = rt << sa << 32; |
2005 break; | 2005 break; |
2006 case SRL: | 2006 case SRL: |
2007 if (rs_reg == 0) { | 2007 if (rs_reg == 0) { |
2008 // Regular logical right shift of a word by a fixed number of | 2008 // Regular logical right shift of a word by a fixed number of |
2009 // bits instruction. RS field is always equal to 0. | 2009 // bits instruction. RS field is always equal to 0. |
2010 *alu_out = (uint32_t)rt_u >> sa; | 2010 // Sign-extend the 32-bit result. |
| 2011 *alu_out = static_cast<int32_t>(static_cast<uint32_t>(rt_u) >> sa); |
2011 } else { | 2012 } else { |
2012 // Logical right-rotate of a word by a fixed number of bits. This | 2013 // Logical right-rotate of a word by a fixed number of bits. This |
2013 // is special case of SRL instruction, added in MIPS32 Release 2. | 2014 // is special case of SRL instruction, added in MIPS32 Release 2. |
2014 // RS field is equal to 00001. | 2015 // RS field is equal to 00001. |
2015 *alu_out = base::bits::RotateRight32((uint32_t)rt_u, sa); | 2016 *alu_out = static_cast<int32_t>( |
| 2017 base::bits::RotateRight32((uint32_t)rt_u, sa)); |
2016 } | 2018 } |
2017 break; | 2019 break; |
2018 case DSRL: | 2020 case DSRL: |
2019 *alu_out = rt_u >> sa; | 2021 *alu_out = rt_u >> sa; |
2020 break; | 2022 break; |
2021 case DSRL32: | 2023 case DSRL32: |
2022 *alu_out = rt_u >> sa >> 32; | 2024 *alu_out = rt_u >> sa >> 32; |
2023 break; | 2025 break; |
2024 case SRA: | 2026 case SRA: |
2025 *alu_out = (int32_t)rt >> sa; | 2027 *alu_out = (int32_t)rt >> sa; |
2026 break; | 2028 break; |
2027 case DSRA: | 2029 case DSRA: |
2028 *alu_out = rt >> sa; | 2030 *alu_out = rt >> sa; |
2029 break; | 2031 break; |
2030 case DSRA32: | 2032 case DSRA32: |
2031 *alu_out = rt >> sa >> 32; | 2033 *alu_out = rt >> sa >> 32; |
2032 break; | 2034 break; |
2033 case SLLV: | 2035 case SLLV: |
2034 *alu_out = (int32_t)rt << rs; | 2036 *alu_out = (int32_t)rt << rs; |
2035 break; | 2037 break; |
2036 case DSLLV: | 2038 case DSLLV: |
2037 *alu_out = rt << rs; | 2039 *alu_out = rt << rs; |
2038 break; | 2040 break; |
2039 case SRLV: | 2041 case SRLV: |
2040 if (sa == 0) { | 2042 if (sa == 0) { |
2041 // Regular logical right-shift of a word by a variable number of | 2043 // Regular logical right-shift of a word by a variable number of |
2042 // bits instruction. SA field is always equal to 0. | 2044 // bits instruction. SA field is always equal to 0. |
2043 *alu_out = (uint32_t)rt_u >> rs; | 2045 *alu_out = static_cast<int32_t>((uint32_t)rt_u >> rs); |
2044 } else { | 2046 } else { |
2045 // Logical right-rotate of a word by a variable number of bits. | 2047 // Logical right-rotate of a word by a variable number of bits. |
2046 // This is special case od SRLV instruction, added in MIPS32 | 2048 // This is special case od SRLV instruction, added in MIPS32 |
2047 // Release 2. SA field is equal to 00001. | 2049 // Release 2. SA field is equal to 00001. |
2048 *alu_out = base::bits::RotateRight32((uint32_t)rt_u, rs_u); | 2050 *alu_out = static_cast<int32_t>( |
| 2051 base::bits::RotateRight32((uint32_t)rt_u, rs_u)); |
2049 } | 2052 } |
2050 break; | 2053 break; |
2051 case DSRLV: | 2054 case DSRLV: |
2052 if (sa == 0) { | 2055 if (sa == 0) { |
2053 // Regular logical right-shift of a word by a variable number of | 2056 // Regular logical right-shift of a word by a variable number of |
2054 // bits instruction. SA field is always equal to 0. | 2057 // bits instruction. SA field is always equal to 0. |
2055 *alu_out = rt_u >> rs; | 2058 *alu_out = rt_u >> rs; |
2056 } else { | 2059 } else { |
2057 // Logical right-rotate of a word by a variable number of bits. | 2060 // Logical right-rotate of a word by a variable number of bits. |
2058 // This is special case od SRLV instruction, added in MIPS32 | 2061 // This is special case od SRLV instruction, added in MIPS32 |
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3447 } | 3450 } |
3448 | 3451 |
3449 | 3452 |
3450 #undef UNSUPPORTED | 3453 #undef UNSUPPORTED |
3451 | 3454 |
3452 } } // namespace v8::internal | 3455 } } // namespace v8::internal |
3453 | 3456 |
3454 #endif // USE_SIMULATOR | 3457 #endif // USE_SIMULATOR |
3455 | 3458 |
3456 #endif // V8_TARGET_ARCH_MIPS64 | 3459 #endif // V8_TARGET_ARCH_MIPS64 |
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