Supports FrameLookup vm test on MIPS

Supports FrameLookup vm test on MIPS

As with the similar CL for ARM, also:
- Supports inline allocation of objects.
- Supports checking of inline cache and instance calls.
- Supports subtype test cache.
- Supports (some) equality checks.
- Supports for (some) conditional branches.
- Supports for pool pointer setup in stubs.
Committed: https://code.google.com/p/dart/source/detail?r=21233

[regis, 2013-04-10 20:53:00]

LGTM

You can leave the branches as is for now, but let's discuss and see how it will
work with more conditions.

https://codereview.chromium.org/14076005/diff/1/runtime/vm/assembler_mips.cc
File runtime/vm/assembler_mips.cc (right):

https://codereview.chromium.org/14076005/diff/1/runtime/vm/assembler_mips.cc#...
runtime/vm/assembler_mips.cc:253: mov(SP, FP);
You can factorize this mov.

https://codereview.chromium.org/14076005/diff/1/runtime/vm/assembler_mips.cc#...
runtime/vm/assembler_mips.cc:297: sw(T0, Address(SP, 3 * kWordSize));
You could save this store if offset != 0:

if (offset == 0) {
  sw(T0, Address(SP, 3 * kWordSize));
} else {
  // Adjust ...

https://codereview.chromium.org/14076005/diff/1/runtime/vm/assembler_mips.h
File runtime/vm/assembler_mips.h (right):

https://codereview.chromium.org/14076005/diff/1/runtime/vm/assembler_mips.h#n...
runtime/vm/assembler_mips.h:574: }
You could forward to AddImmediate(rd, rd, value).

https://codereview.chromium.org/14076005/diff/1/runtime/vm/assembler_mips.h#n...
runtime/vm/assembler_mips.h:700: void BranchOnCondition(Register rd, Label* l,
Condition c);
It would be more natural to have the condition as first parameter, as on Intel
(or maybe second?). It is last on ARM, because each instruction is conditional
and we want the condition to default to 'always', without passing it explicitly.
You could also use the shorter name 'Branch'. Up to you.
But more importantly, why do you need this? It seems that it will map to one
instruction anyway. I would prefer to see the real code being generated, rather
than making it look closer to the ARM version.
If the purpose is to emulate the branch on condition of the flow graph, maybe T8
should be implicit?
You already have BranchEqual, etc... this is getting confusing. Let's chat.

https://codereview.chromium.org/14076005/diff/1/runtime/vm/constants_mips.h
File runtime/vm/constants_mips.h (right):

https://codereview.chromium.org/14076005/diff/1/runtime/vm/constants_mips.h#n...
runtime/vm/constants_mips.h:38: kLastFreeCpuRegister = 25,
You can move this one up to = 21, now that you also use T8 as a tmp.

https://codereview.chromium.org/14076005/diff/1/runtime/vm/constants_mips.h#n...
runtime/vm/constants_mips.h:174: NE,  // not equal
I am not sure this will work once you get other conditions that do not map
directly to a branch.

https://codereview.chromium.org/14076005/diff/1/runtime/vm/intermediate_langu...
File runtime/vm/intermediate_language_mips.cc (right):

https://codereview.chromium.org/14076005/diff/1/runtime/vm/intermediate_langu...
runtime/vm/intermediate_language_mips.cc:1195: // The comparison result is in
CRESREG.
What is CRESREG? CMPRES?

https://codereview.chromium.org/14076005/diff/1/runtime/vm/intermediate_langu...
runtime/vm/intermediate_language_mips.cc:1270: __ BranchOnCondition(CMPRES,
&load_true, true_condition);
It would be clearer to write:
if (kind() == Token::kEQ_STRICT) {
  __ beq(CMPRES, ZR, &load_true);
} else {
  __ bne(CMPRES, ZR, &load_true);
}

[zra, 2013-04-10 21:59:05]

Thanks!

Inlined and removed BranchOnCondition following our discussion.

https://codereview.chromium.org/14076005/diff/1/runtime/vm/assembler_mips.cc
File runtime/vm/assembler_mips.cc (right):

https://codereview.chromium.org/14076005/diff/1/runtime/vm/assembler_mips.cc#...
runtime/vm/assembler_mips.cc:253: mov(SP, FP);
On 2013/04/10 20:53:00, regis wrote:
> You can factorize this mov.

Done.

https://codereview.chromium.org/14076005/diff/1/runtime/vm/assembler_mips.cc#...
runtime/vm/assembler_mips.cc:297: sw(T0, Address(SP, 3 * kWordSize));
On 2013/04/10 20:53:00, regis wrote:
> You could save this store if offset != 0:
> 
> if (offset == 0) {
>   sw(T0, Address(SP, 3 * kWordSize));
> } else {
>   // Adjust ...

Done.

https://codereview.chromium.org/14076005/diff/1/runtime/vm/assembler_mips.h
File runtime/vm/assembler_mips.h (right):

https://codereview.chromium.org/14076005/diff/1/runtime/vm/assembler_mips.h#n...
runtime/vm/assembler_mips.h:574: }
On 2013/04/10 20:53:00, regis wrote:
> You could forward to AddImmediate(rd, rd, value).

Done.

https://codereview.chromium.org/14076005/diff/1/runtime/vm/constants_mips.h
File runtime/vm/constants_mips.h (right):

https://codereview.chromium.org/14076005/diff/1/runtime/vm/constants_mips.h#n...
runtime/vm/constants_mips.h:38: kLastFreeCpuRegister = 25,
On 2013/04/10 20:53:00, regis wrote:
> You can move this one up to = 21, now that you also use T8 as a tmp.

Done.

https://codereview.chromium.org/14076005/diff/1/runtime/vm/intermediate_langu...
File runtime/vm/intermediate_language_mips.cc (right):

https://codereview.chromium.org/14076005/diff/1/runtime/vm/intermediate_langu...
runtime/vm/intermediate_language_mips.cc:1195: // The comparison result is in
CRESREG.
On 2013/04/10 20:53:00, regis wrote:
> What is CRESREG? CMPRES?

Done.

https://codereview.chromium.org/14076005/diff/1/runtime/vm/intermediate_langu...
runtime/vm/intermediate_language_mips.cc:1270: __ BranchOnCondition(CMPRES,
&load_true, true_condition);
On 2013/04/10 20:53:00, regis wrote:
> It would be clearer to write:
> if (kind() == Token::kEQ_STRICT) {
>   __ beq(CMPRES, ZR, &load_true);
> } else {
>   __ bne(CMPRES, ZR, &load_true);
> }

Done.

[zra, 2013-04-10 22:00:05]

Committed patchset #3 manually as r21233 (presubmit successful).