Port of optimized ICs for external and pixel arrays from ia32 to ARM.

src/arm/constants-arm.h

 // Copyright 2010 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 61 matching lines @@
 # define CAN_USE_THUMB_INSTRUCTIONS 1
 #endif
 
 namespace assembler {
 namespace arm {
 
 // Number of registers in normal ARM mode.
 static const int kNumRegisters = 16;
 
 // VFP support.
-static const int kNumVFPRegisters = 48;
+static const int kNumVFPSingleRegisters = 32;
+static const int kNumVFPDoubleRegisters = 16;
+static const int kNumVFPRegisters =
+    kNumVFPSingleRegisters + kNumVFPDoubleRegisters;
 
 // PC is register 15.
 static const int kPCRegister = 15;
 static const int kNoRegister = -1;
 
 // Defines constants and accessor classes to assemble, disassemble and
 // simulate ARM instructions.
 //
 // Section references in the code refer to the "ARM Architecture Reference
 // Manual" from July 2005 (available at http://www.arm.com/miscPDFs/14128.pdf)
@@ skipping 149 matching lines @@
   // Vn(19-16) | Vd(15-12) |  Vm(3-0)
   inline int VnField() const { return Bits(19, 16); }
   inline int VmField() const { return Bits(3, 0); }
   inline int VdField() const { return Bits(15, 12); }
   inline int NField() const { return Bit(7); }
   inline int MField() const { return Bit(5); }
   inline int DField() const { return Bit(22); }
   inline int RtField() const { return Bits(15, 12); }
   inline int PField() const { return Bit(24); }
   inline int UField() const { return Bit(23); }
+  inline int Opc1Field() const { return (Bit(23) << 2) | Bits(21, 20); }
+  inline int Opc2Field() const { return Bits(19, 16); }
+  inline int Opc3Field() const { return Bits(7, 6); }
+  inline int SzField() const { return Bit(8); }
+  inline int VLField() const { return Bit(20); }
+  inline int VCField() const { return Bit(8); }
+  inline int VAField() const { return Bits(23, 21); }
+  inline int VBField() const { return Bits(6, 5); }
 
   // Fields used in Data processing instructions
   inline Opcode OpcodeField() const {
     return static_cast<Opcode>(Bits(24, 21));
   }
   inline int SField() const { return Bit(20); }
     // with register
   inline int RmField() const { return Bits(3, 0); }
   inline Shift ShiftField() const { return static_cast<Shift>(Bits(6, 5)); }
   inline int RegShiftField() const { return Bit(4); }
@@ skipping 70 matching lines @@
 
  private:
   static const char* names_[kNumRegisters];
   static const RegisterAlias aliases_[];
 };
 
 // Helper functions for converting between VFP register numbers and names.
 class VFPRegisters {
  public:
   // Return the name of the register.
-  static const char* Name(int reg);
+  static const char* Name(int reg, bool is_double);
+
+  // Lookup the register number for the name provided.
+  // Set flag pointed by is_double to true if register
+  // is double-precision.
+  static int Number(const char* name, bool* is_double);
 
  private:
   static const char* names_[kNumVFPRegisters];
 };
 
 
 } }  // namespace assembler::arm
 
 #endif  // V8_ARM_CONSTANTS_ARM_H_