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Issue 9455088: Remove static initializers in v8. (Closed) Base URL: http://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Address Florian's comments. Created 8 years, 9 months ago
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1 // Copyright 2011 the V8 project authors. All rights reserved. 1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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27 27
28 #include <assert.h> 28 #include <assert.h>
29 #include <stdio.h> 29 #include <stdio.h>
30 #include <stdarg.h> 30 #include <stdarg.h>
31 31
32 #include "v8.h" 32 #include "v8.h"
33 33
34 #if defined(V8_TARGET_ARCH_X64) 34 #if defined(V8_TARGET_ARCH_X64)
35 35
36 #include "disasm.h" 36 #include "disasm.h"
37 #include "lazy-instance.h"
37 38
38 namespace disasm { 39 namespace disasm {
39 40
40 enum OperandType { 41 enum OperandType {
41 UNSET_OP_ORDER = 0, 42 UNSET_OP_ORDER = 0,
42 // Operand size decides between 16, 32 and 64 bit operands. 43 // Operand size decides between 16, 32 and 64 bit operands.
43 REG_OPER_OP_ORDER = 1, // Register destination, operand source. 44 REG_OPER_OP_ORDER = 1, // Register destination, operand source.
44 OPER_REG_OP_ORDER = 2, // Operand destination, register source. 45 OPER_REG_OP_ORDER = 2, // Operand destination, register source.
45 // Fixed 8-bit operands. 46 // Fixed 8-bit operands.
46 BYTE_SIZE_OPERAND_FLAG = 4, 47 BYTE_SIZE_OPERAND_FLAG = 4,
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262 void InstructionTable::AddJumpConditionalShort() { 263 void InstructionTable::AddJumpConditionalShort() {
263 for (byte b = 0x70; b <= 0x7F; b++) { 264 for (byte b = 0x70; b <= 0x7F; b++) {
264 InstructionDesc* id = &instructions_[b]; 265 InstructionDesc* id = &instructions_[b];
265 ASSERT_EQ(NO_INSTR, id->type); // Information not already entered 266 ASSERT_EQ(NO_INSTR, id->type); // Information not already entered
266 id->mnem = NULL; // Computed depending on condition code. 267 id->mnem = NULL; // Computed depending on condition code.
267 id->type = JUMP_CONDITIONAL_SHORT_INSTR; 268 id->type = JUMP_CONDITIONAL_SHORT_INSTR;
268 } 269 }
269 } 270 }
270 271
271 272
272 static InstructionTable instruction_table; 273 static v8::internal::LazyInstance<InstructionTable>::type instruction_table =
274 LAZY_INSTANCE_INITIALIZER;
273 275
274 276
275 static InstructionDesc cmov_instructions[16] = { 277 static InstructionDesc cmov_instructions[16] = {
276 {"cmovo", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false}, 278 {"cmovo", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
277 {"cmovno", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false}, 279 {"cmovno", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
278 {"cmovc", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false}, 280 {"cmovc", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
279 {"cmovnc", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false}, 281 {"cmovnc", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
280 {"cmovz", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false}, 282 {"cmovz", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
281 {"cmovnz", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false}, 283 {"cmovnz", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
282 {"cmovna", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false}, 284 {"cmovna", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
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1331 setRex(current); 1333 setRex(current);
1332 if (rex_w()) AppendToBuffer("REX.W "); 1334 if (rex_w()) AppendToBuffer("REX.W ");
1333 } else if ((current & 0xFE) == 0xF2) { // Group 1 prefix (0xF2 or 0xF3). 1335 } else if ((current & 0xFE) == 0xF2) { // Group 1 prefix (0xF2 or 0xF3).
1334 group_1_prefix_ = current; 1336 group_1_prefix_ = current;
1335 } else { // Not a prefix - an opcode. 1337 } else { // Not a prefix - an opcode.
1336 break; 1338 break;
1337 } 1339 }
1338 data++; 1340 data++;
1339 } 1341 }
1340 1342
1341 const InstructionDesc& idesc = instruction_table.Get(current); 1343 const InstructionDesc& idesc = instruction_table.Get().Get(current);
1342 byte_size_operand_ = idesc.byte_size_operation; 1344 byte_size_operand_ = idesc.byte_size_operation;
1343 switch (idesc.type) { 1345 switch (idesc.type) {
1344 case ZERO_OPERANDS_INSTR: 1346 case ZERO_OPERANDS_INSTR:
1345 if (current >= 0xA4 && current <= 0xA7) { 1347 if (current >= 0xA4 && current <= 0xA7) {
1346 // String move or compare operations. 1348 // String move or compare operations.
1347 if (group_1_prefix_ == REP_PREFIX) { 1349 if (group_1_prefix_ == REP_PREFIX) {
1348 // REP. 1350 // REP.
1349 AppendToBuffer("rep "); 1351 AppendToBuffer("rep ");
1350 } 1352 }
1351 if (rex_w()) AppendToBuffer("REX.W "); 1353 if (rex_w()) AppendToBuffer("REX.W ");
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1841 for (int i = 6 - static_cast<int>(pc - prev_pc); i >= 0; i--) { 1843 for (int i = 6 - static_cast<int>(pc - prev_pc); i >= 0; i--) {
1842 fprintf(f, " "); 1844 fprintf(f, " ");
1843 } 1845 }
1844 fprintf(f, " %s\n", buffer.start()); 1846 fprintf(f, " %s\n", buffer.start());
1845 } 1847 }
1846 } 1848 }
1847 1849
1848 } // namespace disasm 1850 } // namespace disasm
1849 1851
1850 #endif // V8_TARGET_ARCH_X64 1852 #endif // V8_TARGET_ARCH_X64
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