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1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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2284 break; | 2284 break; |
2285 // Unimplemented opcodes raised an error in the configuration step before, | 2285 // Unimplemented opcodes raised an error in the configuration step before, |
2286 // so we can use the default here to set the destination register in common | 2286 // so we can use the default here to set the destination register in common |
2287 // cases. | 2287 // cases. |
2288 default: | 2288 default: |
2289 set_register(rd_reg, alu_out); | 2289 set_register(rd_reg, alu_out); |
2290 }; | 2290 }; |
2291 } | 2291 } |
2292 | 2292 |
2293 | 2293 |
2294 // Type 2: instructions using a 16 bytes immediate. (eg: addi, beq). | 2294 // Type 2: instructions using a 16 bytes immediate. (e.g. addi, beq). |
2295 void Simulator::DecodeTypeImmediate(Instruction* instr) { | 2295 void Simulator::DecodeTypeImmediate(Instruction* instr) { |
2296 // Instruction fields. | 2296 // Instruction fields. |
2297 Opcode op = instr->OpcodeFieldRaw(); | 2297 Opcode op = instr->OpcodeFieldRaw(); |
2298 int32_t rs = get_register(instr->RsValue()); | 2298 int32_t rs = get_register(instr->RsValue()); |
2299 uint32_t rs_u = static_cast<uint32_t>(rs); | 2299 uint32_t rs_u = static_cast<uint32_t>(rs); |
2300 int32_t rt_reg = instr->RtValue(); // Destination register. | 2300 int32_t rt_reg = instr->RtValue(); // Destination register. |
2301 int32_t rt = get_register(rt_reg); | 2301 int32_t rt = get_register(rt_reg); |
2302 int16_t imm16 = instr->Imm16Value(); | 2302 int16_t imm16 = instr->Imm16Value(); |
2303 | 2303 |
2304 int32_t ft_reg = instr->FtValue(); // Destination register. | 2304 int32_t ft_reg = instr->FtValue(); // Destination register. |
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2607 BranchDelayInstructionDecode(branch_delay_instr); | 2607 BranchDelayInstructionDecode(branch_delay_instr); |
2608 } | 2608 } |
2609 | 2609 |
2610 // If needed update pc after the branch delay execution. | 2610 // If needed update pc after the branch delay execution. |
2611 if (next_pc != bad_ra) { | 2611 if (next_pc != bad_ra) { |
2612 set_pc(next_pc); | 2612 set_pc(next_pc); |
2613 } | 2613 } |
2614 } | 2614 } |
2615 | 2615 |
2616 | 2616 |
2617 // Type 3: instructions using a 26 bytes immediate. (eg: j, jal). | 2617 // Type 3: instructions using a 26 bytes immediate. (e.g. j, jal). |
2618 void Simulator::DecodeTypeJump(Instruction* instr) { | 2618 void Simulator::DecodeTypeJump(Instruction* instr) { |
2619 // Get current pc. | 2619 // Get current pc. |
2620 int32_t current_pc = get_pc(); | 2620 int32_t current_pc = get_pc(); |
2621 // Get unchanged bits of pc. | 2621 // Get unchanged bits of pc. |
2622 int32_t pc_high_bits = current_pc & 0xf0000000; | 2622 int32_t pc_high_bits = current_pc & 0xf0000000; |
2623 // Next pc. | 2623 // Next pc. |
2624 int32_t next_pc = pc_high_bits | (instr->Imm26Value() << 2); | 2624 int32_t next_pc = pc_high_bits | (instr->Imm26Value() << 2); |
2625 | 2625 |
2626 // Execute branch delay slot. | 2626 // Execute branch delay slot. |
2627 // We don't check for end_sim_pc. First it should not be met as the current pc | 2627 // We don't check for end_sim_pc. First it should not be met as the current pc |
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2827 } | 2827 } |
2828 | 2828 |
2829 | 2829 |
2830 #undef UNSUPPORTED | 2830 #undef UNSUPPORTED |
2831 | 2831 |
2832 } } // namespace v8::internal | 2832 } } // namespace v8::internal |
2833 | 2833 |
2834 #endif // USE_SIMULATOR | 2834 #endif // USE_SIMULATOR |
2835 | 2835 |
2836 #endif // V8_TARGET_ARCH_MIPS | 2836 #endif // V8_TARGET_ARCH_MIPS |
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