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1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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295 }; | 295 }; |
296 break; | 296 break; |
297 case COP1: // Coprocessor instructions. | 297 case COP1: // Coprocessor instructions. |
298 switch (RsFieldRawNoAssert()) { | 298 switch (RsFieldRawNoAssert()) { |
299 case BC1: // Branch on coprocessor condition. | 299 case BC1: // Branch on coprocessor condition. |
300 return kImmediateType; | 300 return kImmediateType; |
301 default: | 301 default: |
302 return kRegisterType; | 302 return kRegisterType; |
303 }; | 303 }; |
304 break; | 304 break; |
305 // 16 bits Immediate type instructions. eg: addi dest, src, imm16. | 305 // 16 bits Immediate type instructions. e.g.: addi dest, src, imm16. |
306 case REGIMM: | 306 case REGIMM: |
307 case BEQ: | 307 case BEQ: |
308 case BNE: | 308 case BNE: |
309 case BLEZ: | 309 case BLEZ: |
310 case BGTZ: | 310 case BGTZ: |
311 case ADDI: | 311 case ADDI: |
312 case ADDIU: | 312 case ADDIU: |
313 case SLTI: | 313 case SLTI: |
314 case SLTIU: | 314 case SLTIU: |
315 case ANDI: | 315 case ANDI: |
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330 case SB: | 330 case SB: |
331 case SH: | 331 case SH: |
332 case SWL: | 332 case SWL: |
333 case SW: | 333 case SW: |
334 case SWR: | 334 case SWR: |
335 case LWC1: | 335 case LWC1: |
336 case LDC1: | 336 case LDC1: |
337 case SWC1: | 337 case SWC1: |
338 case SDC1: | 338 case SDC1: |
339 return kImmediateType; | 339 return kImmediateType; |
340 // 26 bits immediate type instructions. eg: j imm26. | 340 // 26 bits immediate type instructions. e.g.: j imm26. |
341 case J: | 341 case J: |
342 case JAL: | 342 case JAL: |
343 return kJumpType; | 343 return kJumpType; |
344 default: | 344 default: |
345 return kUnsupported; | 345 return kUnsupported; |
346 }; | 346 }; |
347 return kUnsupported; | 347 return kUnsupported; |
348 } | 348 } |
349 | 349 |
350 | 350 |
351 } } // namespace v8::internal | 351 } } // namespace v8::internal |
352 | 352 |
353 #endif // V8_TARGET_ARCH_MIPS | 353 #endif // V8_TARGET_ARCH_MIPS |
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