Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(324)

Side by Side Diff: src/cpu-arm.cc

Issue 92068: Move backend specific files to separate directories. (Closed)
Patch Set: Added CPPPATH flag and made all includes use same base path. Created 11 years, 8 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
« no previous file with comments | « src/constants-arm.h ('k') | src/cpu-ia32.cc » ('j') | no next file with comments »
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
(Empty)
1 // Copyright 2006-2008 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are
4 // met:
5 //
6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided
11 // with the distribution.
12 // * Neither the name of Google Inc. nor the names of its
13 // contributors may be used to endorse or promote products derived
14 // from this software without specific prior written permission.
15 //
16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
28 // CPU specific code for arm independent of OS goes here.
29 #if defined(__arm__)
30 #include <sys/syscall.h> // for cache flushing.
31 #endif
32
33 #include "v8.h"
34
35 #include "cpu.h"
36
37 namespace v8 { namespace internal {
38
39 void CPU::Setup() {
40 // Nothing to do.
41 }
42
43
44 void CPU::FlushICache(void* start, size_t size) {
45 #if !defined (__arm__)
46 // Not generating ARM instructions for C-code. This means that we are
47 // building an ARM emulator based target. No I$ flushes are necessary.
48 #else
49 // Ideally, we would call
50 // syscall(__ARM_NR_cacheflush, start,
51 // reinterpret_cast<intptr_t>(start) + size, 0);
52 // however, syscall(int, ...) is not supported on all platforms, especially
53 // not when using EABI, so we call the __ARM_NR_cacheflush syscall directly.
54
55 register uint32_t beg asm("a1") = reinterpret_cast<uint32_t>(start);
56 register uint32_t end asm("a2") =
57 reinterpret_cast<uint32_t>(start) + size;
58 register uint32_t flg asm("a3") = 0;
59 #ifdef __ARM_EABI__
60 register uint32_t scno asm("r7") = __ARM_NR_cacheflush;
61 #if defined (__arm__) && !defined(__thumb__)
62 // __arm__ may be defined in thumb mode.
63 asm volatile(
64 "swi 0x0"
65 : "=r" (beg)
66 : "0" (beg), "r" (end), "r" (flg), "r" (scno));
67 #else
68 asm volatile(
69 "@ Enter ARM Mode \n\t"
70 "adr r3, 1f \n\t"
71 "bx r3 \n\t"
72 ".ALIGN 4 \n\t"
73 ".ARM \n"
74 "1: swi 0x0 \n\t"
75 "@ Enter THUMB Mode\n\t"
76 "adr r3, 2f+1 \n\t"
77 "bx r3 \n\t"
78 ".THUMB \n"
79 "2: \n\t"
80 : "=r" (beg)
81 : "0" (beg), "r" (end), "r" (flg), "r" (scno)
82 : "r3");
83 #endif
84 #else
85 #if defined (__arm__) && !defined(__thumb__)
86 // __arm__ may be defined in thumb mode.
87 asm volatile(
88 "swi %1"
89 : "=r" (beg)
90 : "i" (__ARM_NR_cacheflush), "0" (beg), "r" (end), "r" (flg));
91 #else
92 // Do not use the value of __ARM_NR_cacheflush in the inline assembly
93 // below, because the thumb mode value would be used, which would be
94 // wrong, since we switch to ARM mode before executing the swi instruction
95 asm volatile(
96 "@ Enter ARM Mode \n\t"
97 "adr r3, 1f \n\t"
98 "bx r3 \n\t"
99 ".ALIGN 4 \n\t"
100 ".ARM \n"
101 "1: swi 0x9f0002 \n"
102 "@ Enter THUMB Mode\n\t"
103 "adr r3, 2f+1 \n\t"
104 "bx r3 \n\t"
105 ".THUMB \n"
106 "2: \n\t"
107 : "=r" (beg)
108 : "0" (beg), "r" (end), "r" (flg)
109 : "r3");
110 #endif
111 #endif
112 #endif
113 }
114
115
116 void CPU::DebugBreak() {
117 #if !defined (__arm__)
118 UNIMPLEMENTED(); // when building ARM emulator target
119 #else
120 asm volatile("bkpt 0");
121 #endif
122 }
123
124 } } // namespace v8::internal
OLDNEW
« no previous file with comments | « src/constants-arm.h ('k') | src/cpu-ia32.cc » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698