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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | |
2 // All Rights Reserved. | |
3 // | |
4 // Redistribution and use in source and binary forms, with or without | |
5 // modification, are permitted provided that the following conditions | |
6 // are met: | |
7 // | |
8 // - Redistributions of source code must retain the above copyright notice, | |
9 // this list of conditions and the following disclaimer. | |
10 // | |
11 // - Redistribution in binary form must reproduce the above copyright | |
12 // notice, this list of conditions and the following disclaimer in the | |
13 // documentation and/or other materials provided with the | |
14 // distribution. | |
15 // | |
16 // - Neither the name of Sun Microsystems or the names of contributors may | |
17 // be used to endorse or promote products derived from this software without | |
18 // specific prior written permission. | |
19 // | |
20 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
21 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
22 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS | |
23 // FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE | |
24 // COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, | |
25 // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
26 // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
27 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
28 // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, | |
29 // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
30 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED | |
31 // OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 | |
33 // The original source code covered by the above license above has been modified | |
34 // significantly by Google Inc. | |
35 // Copyright 2006-2008 the V8 project authors. All rights reserved. | |
36 | |
37 // A light-weight ARM Assembler | |
38 // Generates user mode instructions for the ARM architecture up to version 5 | |
39 | |
40 #ifndef V8_ASSEMBLER_ARM_H_ | |
41 #define V8_ASSEMBLER_ARM_H_ | |
42 | |
43 #include "assembler.h" | |
44 | |
45 namespace v8 { namespace internal { | |
46 | |
47 // CPU Registers. | |
48 // | |
49 // 1) We would prefer to use an enum, but enum values are assignment- | |
50 // compatible with int, which has caused code-generation bugs. | |
51 // | |
52 // 2) We would prefer to use a class instead of a struct but we don't like | |
53 // the register initialization to depend on the particular initialization | |
54 // order (which appears to be different on OS X, Linux, and Windows for the | |
55 // installed versions of C++ we tried). Using a struct permits C-style | |
56 // "initialization". Also, the Register objects cannot be const as this | |
57 // forces initialization stubs in MSVC, making us dependent on initialization | |
58 // order. | |
59 // | |
60 // 3) By not using an enum, we are possibly preventing the compiler from | |
61 // doing certain constant folds, which may significantly reduce the | |
62 // code generated for some assembly instructions (because they boil down | |
63 // to a few constants). If this is a problem, we could change the code | |
64 // such that we use an enum in optimized mode, and the struct in debug | |
65 // mode. This way we get the compile-time error checking in debug mode | |
66 // and best performance in optimized code. | |
67 // | |
68 // Core register | |
69 struct Register { | |
70 bool is_valid() const { return 0 <= code_ && code_ < 16; } | |
71 bool is(Register reg) const { return code_ == reg.code_; } | |
72 int code() const { | |
73 ASSERT(is_valid()); | |
74 return code_; | |
75 } | |
76 int bit() const { | |
77 ASSERT(is_valid()); | |
78 return 1 << code_; | |
79 } | |
80 | |
81 // (unfortunately we can't make this private in a struct) | |
82 int code_; | |
83 }; | |
84 | |
85 | |
86 const int kNumRegisters = 16; | |
87 | |
88 extern Register no_reg; | |
89 extern Register r0; | |
90 extern Register r1; | |
91 extern Register r2; | |
92 extern Register r3; | |
93 extern Register r4; | |
94 extern Register r5; | |
95 extern Register r6; | |
96 extern Register r7; | |
97 extern Register r8; | |
98 extern Register r9; | |
99 extern Register r10; | |
100 extern Register fp; | |
101 extern Register ip; | |
102 extern Register sp; | |
103 extern Register lr; | |
104 extern Register pc; | |
105 | |
106 | |
107 // Coprocessor register | |
108 struct CRegister { | |
109 bool is_valid() const { return 0 <= code_ && code_ < 16; } | |
110 bool is(CRegister creg) const { return code_ == creg.code_; } | |
111 int code() const { | |
112 ASSERT(is_valid()); | |
113 return code_; | |
114 } | |
115 int bit() const { | |
116 ASSERT(is_valid()); | |
117 return 1 << code_; | |
118 } | |
119 | |
120 // (unfortunately we can't make this private in a struct) | |
121 int code_; | |
122 }; | |
123 | |
124 | |
125 extern CRegister no_creg; | |
126 extern CRegister cr0; | |
127 extern CRegister cr1; | |
128 extern CRegister cr2; | |
129 extern CRegister cr3; | |
130 extern CRegister cr4; | |
131 extern CRegister cr5; | |
132 extern CRegister cr6; | |
133 extern CRegister cr7; | |
134 extern CRegister cr8; | |
135 extern CRegister cr9; | |
136 extern CRegister cr10; | |
137 extern CRegister cr11; | |
138 extern CRegister cr12; | |
139 extern CRegister cr13; | |
140 extern CRegister cr14; | |
141 extern CRegister cr15; | |
142 | |
143 | |
144 // Coprocessor number | |
145 enum Coprocessor { | |
146 p0 = 0, | |
147 p1 = 1, | |
148 p2 = 2, | |
149 p3 = 3, | |
150 p4 = 4, | |
151 p5 = 5, | |
152 p6 = 6, | |
153 p7 = 7, | |
154 p8 = 8, | |
155 p9 = 9, | |
156 p10 = 10, | |
157 p11 = 11, | |
158 p12 = 12, | |
159 p13 = 13, | |
160 p14 = 14, | |
161 p15 = 15 | |
162 }; | |
163 | |
164 | |
165 // Condition field in instructions | |
166 enum Condition { | |
167 eq = 0 << 28, | |
168 ne = 1 << 28, | |
169 cs = 2 << 28, | |
170 hs = 2 << 28, | |
171 cc = 3 << 28, | |
172 lo = 3 << 28, | |
173 mi = 4 << 28, | |
174 pl = 5 << 28, | |
175 vs = 6 << 28, | |
176 vc = 7 << 28, | |
177 hi = 8 << 28, | |
178 ls = 9 << 28, | |
179 ge = 10 << 28, | |
180 lt = 11 << 28, | |
181 gt = 12 << 28, | |
182 le = 13 << 28, | |
183 al = 14 << 28 | |
184 }; | |
185 | |
186 | |
187 // Returns the equivalent of !cc. | |
188 INLINE(Condition NegateCondition(Condition cc)); | |
189 | |
190 | |
191 // Corresponds to transposing the operands of a comparison. | |
192 inline Condition ReverseCondition(Condition cc) { | |
193 switch (cc) { | |
194 case lo: | |
195 return hi; | |
196 case hi: | |
197 return lo; | |
198 case hs: | |
199 return ls; | |
200 case ls: | |
201 return hs; | |
202 case lt: | |
203 return gt; | |
204 case gt: | |
205 return lt; | |
206 case ge: | |
207 return le; | |
208 case le: | |
209 return ge; | |
210 default: | |
211 return cc; | |
212 }; | |
213 } | |
214 | |
215 | |
216 // Branch hints are not used on the ARM. They are defined so that they can | |
217 // appear in shared function signatures, but will be ignored in ARM | |
218 // implementations. | |
219 enum Hint { no_hint }; | |
220 | |
221 // Hints are not used on the arm. Negating is trivial. | |
222 inline Hint NegateHint(Hint ignored) { return no_hint; } | |
223 | |
224 | |
225 // ----------------------------------------------------------------------------- | |
226 // Addressing modes and instruction variants | |
227 | |
228 // Shifter operand shift operation | |
229 enum ShiftOp { | |
230 LSL = 0 << 5, | |
231 LSR = 1 << 5, | |
232 ASR = 2 << 5, | |
233 ROR = 3 << 5, | |
234 RRX = -1 | |
235 }; | |
236 | |
237 | |
238 // Condition code updating mode | |
239 enum SBit { | |
240 SetCC = 1 << 20, // set condition code | |
241 LeaveCC = 0 << 20 // leave condition code unchanged | |
242 }; | |
243 | |
244 | |
245 // Status register selection | |
246 enum SRegister { | |
247 CPSR = 0 << 22, | |
248 SPSR = 1 << 22 | |
249 }; | |
250 | |
251 | |
252 // Status register fields | |
253 enum SRegisterField { | |
254 CPSR_c = CPSR | 1 << 16, | |
255 CPSR_x = CPSR | 1 << 17, | |
256 CPSR_s = CPSR | 1 << 18, | |
257 CPSR_f = CPSR | 1 << 19, | |
258 SPSR_c = SPSR | 1 << 16, | |
259 SPSR_x = SPSR | 1 << 17, | |
260 SPSR_s = SPSR | 1 << 18, | |
261 SPSR_f = SPSR | 1 << 19 | |
262 }; | |
263 | |
264 // Status register field mask (or'ed SRegisterField enum values) | |
265 typedef uint32_t SRegisterFieldMask; | |
266 | |
267 | |
268 // Memory operand addressing mode | |
269 enum AddrMode { | |
270 // bit encoding P U W | |
271 Offset = (8|4|0) << 21, // offset (without writeback to base) | |
272 PreIndex = (8|4|1) << 21, // pre-indexed addressing with writeback | |
273 PostIndex = (0|4|0) << 21, // post-indexed addressing with writeback | |
274 NegOffset = (8|0|0) << 21, // negative offset (without writeback to base) | |
275 NegPreIndex = (8|0|1) << 21, // negative pre-indexed with writeback | |
276 NegPostIndex = (0|0|0) << 21 // negative post-indexed with writeback | |
277 }; | |
278 | |
279 | |
280 // Load/store multiple addressing mode | |
281 enum BlockAddrMode { | |
282 // bit encoding P U W | |
283 da = (0|0|0) << 21, // decrement after | |
284 ia = (0|4|0) << 21, // increment after | |
285 db = (8|0|0) << 21, // decrement before | |
286 ib = (8|4|0) << 21, // increment before | |
287 da_w = (0|0|1) << 21, // decrement after with writeback to base | |
288 ia_w = (0|4|1) << 21, // increment after with writeback to base | |
289 db_w = (8|0|1) << 21, // decrement before with writeback to base | |
290 ib_w = (8|4|1) << 21 // increment before with writeback to base | |
291 }; | |
292 | |
293 | |
294 // Coprocessor load/store operand size | |
295 enum LFlag { | |
296 Long = 1 << 22, // long load/store coprocessor | |
297 Short = 0 << 22 // short load/store coprocessor | |
298 }; | |
299 | |
300 | |
301 // ----------------------------------------------------------------------------- | |
302 // Machine instruction Operands | |
303 | |
304 // Class Operand represents a shifter operand in data processing instructions | |
305 class Operand BASE_EMBEDDED { | |
306 public: | |
307 // immediate | |
308 INLINE(explicit Operand(int32_t immediate, | |
309 RelocInfo::Mode rmode = RelocInfo::NONE)); | |
310 INLINE(explicit Operand(const ExternalReference& f)); | |
311 INLINE(explicit Operand(const char* s)); | |
312 INLINE(explicit Operand(Object** opp)); | |
313 INLINE(explicit Operand(Context** cpp)); | |
314 explicit Operand(Handle<Object> handle); | |
315 INLINE(explicit Operand(Smi* value)); | |
316 | |
317 // rm | |
318 INLINE(explicit Operand(Register rm)); | |
319 | |
320 // rm <shift_op> shift_imm | |
321 explicit Operand(Register rm, ShiftOp shift_op, int shift_imm); | |
322 | |
323 // rm <shift_op> rs | |
324 explicit Operand(Register rm, ShiftOp shift_op, Register rs); | |
325 | |
326 // Return true if this is a register operand. | |
327 INLINE(bool is_reg() const); | |
328 | |
329 Register rm() const { return rm_; } | |
330 | |
331 private: | |
332 Register rm_; | |
333 Register rs_; | |
334 ShiftOp shift_op_; | |
335 int shift_imm_; // valid if rm_ != no_reg && rs_ == no_reg | |
336 int32_t imm32_; // valid if rm_ == no_reg | |
337 RelocInfo::Mode rmode_; | |
338 | |
339 friend class Assembler; | |
340 }; | |
341 | |
342 | |
343 // Class MemOperand represents a memory operand in load and store instructions | |
344 class MemOperand BASE_EMBEDDED { | |
345 public: | |
346 // [rn +/- offset] Offset/NegOffset | |
347 // [rn +/- offset]! PreIndex/NegPreIndex | |
348 // [rn], +/- offset PostIndex/NegPostIndex | |
349 // offset is any signed 32-bit value; offset is first loaded to register ip if | |
350 // it does not fit the addressing mode (12-bit unsigned and sign bit) | |
351 explicit MemOperand(Register rn, int32_t offset = 0, AddrMode am = Offset); | |
352 | |
353 // [rn +/- rm] Offset/NegOffset | |
354 // [rn +/- rm]! PreIndex/NegPreIndex | |
355 // [rn], +/- rm PostIndex/NegPostIndex | |
356 explicit MemOperand(Register rn, Register rm, AddrMode am = Offset); | |
357 | |
358 // [rn +/- rm <shift_op> shift_imm] Offset/NegOffset | |
359 // [rn +/- rm <shift_op> shift_imm]! PreIndex/NegPreIndex | |
360 // [rn], +/- rm <shift_op> shift_imm PostIndex/NegPostIndex | |
361 explicit MemOperand(Register rn, Register rm, | |
362 ShiftOp shift_op, int shift_imm, AddrMode am = Offset); | |
363 | |
364 private: | |
365 Register rn_; // base | |
366 Register rm_; // register offset | |
367 int32_t offset_; // valid if rm_ == no_reg | |
368 ShiftOp shift_op_; | |
369 int shift_imm_; // valid if rm_ != no_reg && rs_ == no_reg | |
370 AddrMode am_; // bits P, U, and W | |
371 | |
372 friend class Assembler; | |
373 }; | |
374 | |
375 | |
376 typedef int32_t Instr; | |
377 | |
378 | |
379 class Assembler : public Malloced { | |
380 public: | |
381 // Create an assembler. Instructions and relocation information are emitted | |
382 // into a buffer, with the instructions starting from the beginning and the | |
383 // relocation information starting from the end of the buffer. See CodeDesc | |
384 // for a detailed comment on the layout (globals.h). | |
385 // | |
386 // If the provided buffer is NULL, the assembler allocates and grows its own | |
387 // buffer, and buffer_size determines the initial buffer size. The buffer is | |
388 // owned by the assembler and deallocated upon destruction of the assembler. | |
389 // | |
390 // If the provided buffer is not NULL, the assembler uses the provided buffer | |
391 // for code generation and assumes its size to be buffer_size. If the buffer | |
392 // is too small, a fatal error occurs. No deallocation of the buffer is done | |
393 // upon destruction of the assembler. | |
394 Assembler(void* buffer, int buffer_size); | |
395 ~Assembler(); | |
396 | |
397 // GetCode emits any pending (non-emitted) code and fills the descriptor | |
398 // desc. GetCode() is idempotent; it returns the same result if no other | |
399 // Assembler functions are invoked in between GetCode() calls. | |
400 void GetCode(CodeDesc* desc); | |
401 | |
402 // Label operations & relative jumps (PPUM Appendix D) | |
403 // | |
404 // Takes a branch opcode (cc) and a label (L) and generates | |
405 // either a backward branch or a forward branch and links it | |
406 // to the label fixup chain. Usage: | |
407 // | |
408 // Label L; // unbound label | |
409 // j(cc, &L); // forward branch to unbound label | |
410 // bind(&L); // bind label to the current pc | |
411 // j(cc, &L); // backward branch to bound label | |
412 // bind(&L); // illegal: a label may be bound only once | |
413 // | |
414 // Note: The same Label can be used for forward and backward branches | |
415 // but it may be bound only once. | |
416 | |
417 void bind(Label* L); // binds an unbound label L to the current code position | |
418 | |
419 // Returns the branch offset to the given label from the current code position | |
420 // Links the label to the current position if it is still unbound | |
421 // Manages the jump elimination optimization if the second parameter is true. | |
422 int branch_offset(Label* L, bool jump_elimination_allowed); | |
423 | |
424 // Return the address in the constant pool of the code target address used by | |
425 // the branch/call instruction at pc. | |
426 INLINE(static Address target_address_address_at(Address pc)); | |
427 | |
428 // Read/Modify the code target address in the branch/call instruction at pc. | |
429 INLINE(static Address target_address_at(Address pc)); | |
430 INLINE(static void set_target_address_at(Address pc, Address target)); | |
431 | |
432 // Distance between the instruction referring to the address of the call | |
433 // target (ldr pc, [target addr in const pool]) and the return address | |
434 static const int kTargetAddrToReturnAddrDist = sizeof(Instr); | |
435 | |
436 | |
437 // --------------------------------------------------------------------------- | |
438 // Code generation | |
439 | |
440 // Insert the smallest number of nop instructions | |
441 // possible to align the pc offset to a multiple | |
442 // of m. m must be a power of 2 (>= 4). | |
443 void Align(int m); | |
444 | |
445 // Branch instructions | |
446 void b(int branch_offset, Condition cond = al); | |
447 void bl(int branch_offset, Condition cond = al); | |
448 void blx(int branch_offset); // v5 and above | |
449 void blx(Register target, Condition cond = al); // v5 and above | |
450 void bx(Register target, Condition cond = al); // v5 and above, plus v4t | |
451 | |
452 // Convenience branch instructions using labels | |
453 void b(Label* L, Condition cond = al) { | |
454 b(branch_offset(L, cond == al), cond); | |
455 } | |
456 void b(Condition cond, Label* L) { b(branch_offset(L, cond == al), cond); } | |
457 void bl(Label* L, Condition cond = al) { bl(branch_offset(L, false), cond); } | |
458 void bl(Condition cond, Label* L) { bl(branch_offset(L, false), cond); } | |
459 void blx(Label* L) { blx(branch_offset(L, false)); } // v5 and above | |
460 | |
461 // Data-processing instructions | |
462 void and_(Register dst, Register src1, const Operand& src2, | |
463 SBit s = LeaveCC, Condition cond = al); | |
464 | |
465 void eor(Register dst, Register src1, const Operand& src2, | |
466 SBit s = LeaveCC, Condition cond = al); | |
467 | |
468 void sub(Register dst, Register src1, const Operand& src2, | |
469 SBit s = LeaveCC, Condition cond = al); | |
470 void sub(Register dst, Register src1, Register src2, | |
471 SBit s = LeaveCC, Condition cond = al) { | |
472 sub(dst, src1, Operand(src2), s, cond); | |
473 } | |
474 | |
475 void rsb(Register dst, Register src1, const Operand& src2, | |
476 SBit s = LeaveCC, Condition cond = al); | |
477 | |
478 void add(Register dst, Register src1, const Operand& src2, | |
479 SBit s = LeaveCC, Condition cond = al); | |
480 | |
481 void adc(Register dst, Register src1, const Operand& src2, | |
482 SBit s = LeaveCC, Condition cond = al); | |
483 | |
484 void sbc(Register dst, Register src1, const Operand& src2, | |
485 SBit s = LeaveCC, Condition cond = al); | |
486 | |
487 void rsc(Register dst, Register src1, const Operand& src2, | |
488 SBit s = LeaveCC, Condition cond = al); | |
489 | |
490 void tst(Register src1, const Operand& src2, Condition cond = al); | |
491 void tst(Register src1, Register src2, Condition cond = al) { | |
492 tst(src1, Operand(src2), cond); | |
493 } | |
494 | |
495 void teq(Register src1, const Operand& src2, Condition cond = al); | |
496 | |
497 void cmp(Register src1, const Operand& src2, Condition cond = al); | |
498 void cmp(Register src1, Register src2, Condition cond = al) { | |
499 cmp(src1, Operand(src2), cond); | |
500 } | |
501 | |
502 void cmn(Register src1, const Operand& src2, Condition cond = al); | |
503 | |
504 void orr(Register dst, Register src1, const Operand& src2, | |
505 SBit s = LeaveCC, Condition cond = al); | |
506 void orr(Register dst, Register src1, Register src2, | |
507 SBit s = LeaveCC, Condition cond = al) { | |
508 orr(dst, src1, Operand(src2), s, cond); | |
509 } | |
510 | |
511 void mov(Register dst, const Operand& src, | |
512 SBit s = LeaveCC, Condition cond = al); | |
513 void mov(Register dst, Register src, SBit s = LeaveCC, Condition cond = al) { | |
514 mov(dst, Operand(src), s, cond); | |
515 } | |
516 | |
517 void bic(Register dst, Register src1, const Operand& src2, | |
518 SBit s = LeaveCC, Condition cond = al); | |
519 | |
520 void mvn(Register dst, const Operand& src, | |
521 SBit s = LeaveCC, Condition cond = al); | |
522 | |
523 // Multiply instructions | |
524 | |
525 void mla(Register dst, Register src1, Register src2, Register srcA, | |
526 SBit s = LeaveCC, Condition cond = al); | |
527 | |
528 void mul(Register dst, Register src1, Register src2, | |
529 SBit s = LeaveCC, Condition cond = al); | |
530 | |
531 void smlal(Register dstL, Register dstH, Register src1, Register src2, | |
532 SBit s = LeaveCC, Condition cond = al); | |
533 | |
534 void smull(Register dstL, Register dstH, Register src1, Register src2, | |
535 SBit s = LeaveCC, Condition cond = al); | |
536 | |
537 void umlal(Register dstL, Register dstH, Register src1, Register src2, | |
538 SBit s = LeaveCC, Condition cond = al); | |
539 | |
540 void umull(Register dstL, Register dstH, Register src1, Register src2, | |
541 SBit s = LeaveCC, Condition cond = al); | |
542 | |
543 // Miscellaneous arithmetic instructions | |
544 | |
545 void clz(Register dst, Register src, Condition cond = al); // v5 and above | |
546 | |
547 // Status register access instructions | |
548 | |
549 void mrs(Register dst, SRegister s, Condition cond = al); | |
550 void msr(SRegisterFieldMask fields, const Operand& src, Condition cond = al); | |
551 | |
552 // Load/Store instructions | |
553 void ldr(Register dst, const MemOperand& src, Condition cond = al); | |
554 void str(Register src, const MemOperand& dst, Condition cond = al); | |
555 void ldrb(Register dst, const MemOperand& src, Condition cond = al); | |
556 void strb(Register src, const MemOperand& dst, Condition cond = al); | |
557 void ldrh(Register dst, const MemOperand& src, Condition cond = al); | |
558 void strh(Register src, const MemOperand& dst, Condition cond = al); | |
559 void ldrsb(Register dst, const MemOperand& src, Condition cond = al); | |
560 void ldrsh(Register dst, const MemOperand& src, Condition cond = al); | |
561 | |
562 // Load/Store multiple instructions | |
563 void ldm(BlockAddrMode am, Register base, RegList dst, Condition cond = al); | |
564 void stm(BlockAddrMode am, Register base, RegList src, Condition cond = al); | |
565 | |
566 // Semaphore instructions | |
567 void swp(Register dst, Register src, Register base, Condition cond = al); | |
568 void swpb(Register dst, Register src, Register base, Condition cond = al); | |
569 | |
570 // Exception-generating instructions and debugging support | |
571 void stop(const char* msg); | |
572 | |
573 void bkpt(uint32_t imm16); // v5 and above | |
574 void swi(uint32_t imm24, Condition cond = al); | |
575 | |
576 // Coprocessor instructions | |
577 | |
578 void cdp(Coprocessor coproc, int opcode_1, | |
579 CRegister crd, CRegister crn, CRegister crm, | |
580 int opcode_2, Condition cond = al); | |
581 | |
582 void cdp2(Coprocessor coproc, int opcode_1, | |
583 CRegister crd, CRegister crn, CRegister crm, | |
584 int opcode_2); // v5 and above | |
585 | |
586 void mcr(Coprocessor coproc, int opcode_1, | |
587 Register rd, CRegister crn, CRegister crm, | |
588 int opcode_2 = 0, Condition cond = al); | |
589 | |
590 void mcr2(Coprocessor coproc, int opcode_1, | |
591 Register rd, CRegister crn, CRegister crm, | |
592 int opcode_2 = 0); // v5 and above | |
593 | |
594 void mrc(Coprocessor coproc, int opcode_1, | |
595 Register rd, CRegister crn, CRegister crm, | |
596 int opcode_2 = 0, Condition cond = al); | |
597 | |
598 void mrc2(Coprocessor coproc, int opcode_1, | |
599 Register rd, CRegister crn, CRegister crm, | |
600 int opcode_2 = 0); // v5 and above | |
601 | |
602 void ldc(Coprocessor coproc, CRegister crd, const MemOperand& src, | |
603 LFlag l = Short, Condition cond = al); | |
604 void ldc(Coprocessor coproc, CRegister crd, Register base, int option, | |
605 LFlag l = Short, Condition cond = al); | |
606 | |
607 void ldc2(Coprocessor coproc, CRegister crd, const MemOperand& src, | |
608 LFlag l = Short); // v5 and above | |
609 void ldc2(Coprocessor coproc, CRegister crd, Register base, int option, | |
610 LFlag l = Short); // v5 and above | |
611 | |
612 void stc(Coprocessor coproc, CRegister crd, const MemOperand& dst, | |
613 LFlag l = Short, Condition cond = al); | |
614 void stc(Coprocessor coproc, CRegister crd, Register base, int option, | |
615 LFlag l = Short, Condition cond = al); | |
616 | |
617 void stc2(Coprocessor coproc, CRegister crd, const MemOperand& dst, | |
618 LFlag l = Short); // v5 and above | |
619 void stc2(Coprocessor coproc, CRegister crd, Register base, int option, | |
620 LFlag l = Short); // v5 and above | |
621 | |
622 // Pseudo instructions | |
623 void nop() { mov(r0, Operand(r0)); } | |
624 | |
625 void push(Register src) { | |
626 str(src, MemOperand(sp, 4, NegPreIndex), al); | |
627 } | |
628 | |
629 void pop(Register dst) { | |
630 ldr(dst, MemOperand(sp, 4, PostIndex), al); | |
631 } | |
632 | |
633 void pop() { | |
634 add(sp, sp, Operand(kPointerSize)); | |
635 } | |
636 | |
637 // Load effective address of memory operand x into register dst | |
638 void lea(Register dst, const MemOperand& x, | |
639 SBit s = LeaveCC, Condition cond = al); | |
640 | |
641 // Jump unconditionally to given label. | |
642 void jmp(Label* L) { b(L, al); } | |
643 | |
644 | |
645 // Debugging | |
646 | |
647 // Record a comment relocation entry that can be used by a disassembler. | |
648 // Use --debug_code to enable. | |
649 void RecordComment(const char* msg); | |
650 | |
651 void RecordPosition(int pos); | |
652 void RecordStatementPosition(int pos); | |
653 void WriteRecordedPositions(); | |
654 | |
655 int pc_offset() const { return pc_ - buffer_; } | |
656 int current_position() const { return current_position_; } | |
657 int current_statement_position() const { return current_position_; } | |
658 | |
659 protected: | |
660 int buffer_space() const { return reloc_info_writer.pos() - pc_; } | |
661 | |
662 // Read/patch instructions | |
663 Instr instr_at(byte* pc) { return *reinterpret_cast<Instr*>(pc); } | |
664 void instr_at_put(byte* pc, Instr instr) { | |
665 *reinterpret_cast<Instr*>(pc) = instr; | |
666 } | |
667 Instr instr_at(int pos) { return *reinterpret_cast<Instr*>(buffer_ + pos); } | |
668 void instr_at_put(int pos, Instr instr) { | |
669 *reinterpret_cast<Instr*>(buffer_ + pos) = instr; | |
670 } | |
671 | |
672 // Decode branch instruction at pos and return branch target pos | |
673 int target_at(int pos); | |
674 | |
675 // Patch branch instruction at pos to branch to given branch target pos | |
676 void target_at_put(int pos, int target_pos); | |
677 | |
678 // Check if is time to emit a constant pool for pending reloc info entries | |
679 void CheckConstPool(bool force_emit, bool require_jump); | |
680 | |
681 // Block the emission of the constant pool before pc_offset | |
682 void BlockConstPoolBefore(int pc_offset) { | |
683 if (no_const_pool_before_ < pc_offset) no_const_pool_before_ = pc_offset; | |
684 } | |
685 | |
686 private: | |
687 // Code buffer: | |
688 // The buffer into which code and relocation info are generated. | |
689 byte* buffer_; | |
690 int buffer_size_; | |
691 // True if the assembler owns the buffer, false if buffer is external. | |
692 bool own_buffer_; | |
693 | |
694 // Buffer size and constant pool distance are checked together at regular | |
695 // intervals of kBufferCheckInterval emitted bytes | |
696 static const int kBufferCheckInterval = 1*KB/2; | |
697 int next_buffer_check_; // pc offset of next buffer check | |
698 | |
699 // Code generation | |
700 static const int kInstrSize = sizeof(Instr); // signed size | |
701 // The relocation writer's position is at least kGap bytes below the end of | |
702 // the generated instructions. This is so that multi-instruction sequences do | |
703 // not have to check for overflow. The same is true for writes of large | |
704 // relocation info entries. | |
705 static const int kGap = 32; | |
706 byte* pc_; // the program counter; moves forward | |
707 | |
708 // Constant pool generation | |
709 // Pools are emitted in the instruction stream, preferably after unconditional | |
710 // jumps or after returns from functions (in dead code locations). | |
711 // If a long code sequence does not contain unconditional jumps, it is | |
712 // necessary to emit the constant pool before the pool gets too far from the | |
713 // location it is accessed from. In this case, we emit a jump over the emitted | |
714 // constant pool. | |
715 // Constants in the pool may be addresses of functions that gets relocated; | |
716 // if so, a relocation info entry is associated to the constant pool entry. | |
717 | |
718 // Repeated checking whether the constant pool should be emitted is rather | |
719 // expensive. By default we only check again once a number of instructions | |
720 // has been generated. That also means that the sizing of the buffers is not | |
721 // an exact science, and that we rely on some slop to not overrun buffers. | |
722 static const int kCheckConstIntervalInst = 32; | |
723 static const int kCheckConstInterval = kCheckConstIntervalInst * kInstrSize; | |
724 | |
725 | |
726 // Pools are emitted after function return and in dead code at (more or less) | |
727 // regular intervals of kDistBetweenPools bytes | |
728 static const int kDistBetweenPools = 1*KB; | |
729 | |
730 // Constants in pools are accessed via pc relative addressing, which can | |
731 // reach +/-4KB thereby defining a maximum distance between the instruction | |
732 // and the accessed constant. We satisfy this constraint by limiting the | |
733 // distance between pools. | |
734 static const int kMaxDistBetweenPools = 4*KB - 2*kBufferCheckInterval; | |
735 | |
736 // Emission of the constant pool may be blocked in some code sequences | |
737 int no_const_pool_before_; // block emission before this pc offset | |
738 | |
739 // Keep track of the last emitted pool to guarantee a maximal distance | |
740 int last_const_pool_end_; // pc offset following the last constant pool | |
741 | |
742 // Relocation info generation | |
743 // Each relocation is encoded as a variable size value | |
744 static const int kMaxRelocSize = RelocInfoWriter::kMaxSize; | |
745 RelocInfoWriter reloc_info_writer; | |
746 // Relocation info records are also used during code generation as temporary | |
747 // containers for constants and code target addresses until they are emitted | |
748 // to the constant pool. These pending relocation info records are temporarily | |
749 // stored in a separate buffer until a constant pool is emitted. | |
750 // If every instruction in a long sequence is accessing the pool, we need one | |
751 // pending relocation entry per instruction. | |
752 static const int kMaxNumPRInfo = kMaxDistBetweenPools/kInstrSize; | |
753 RelocInfo prinfo_[kMaxNumPRInfo]; // the buffer of pending relocation info | |
754 int num_prinfo_; // number of pending reloc info entries in the buffer | |
755 | |
756 // The bound position, before this we cannot do instruction elimination. | |
757 int last_bound_pos_; | |
758 | |
759 // source position information | |
760 int current_position_; | |
761 int current_statement_position_; | |
762 int written_position_; | |
763 int written_statement_position_; | |
764 | |
765 // Code emission | |
766 inline void CheckBuffer(); | |
767 void GrowBuffer(); | |
768 inline void emit(Instr x); | |
769 | |
770 // Instruction generation | |
771 void addrmod1(Instr instr, Register rn, Register rd, const Operand& x); | |
772 void addrmod2(Instr instr, Register rd, const MemOperand& x); | |
773 void addrmod3(Instr instr, Register rd, const MemOperand& x); | |
774 void addrmod4(Instr instr, Register rn, RegList rl); | |
775 void addrmod5(Instr instr, CRegister crd, const MemOperand& x); | |
776 | |
777 // Labels | |
778 void print(Label* L); | |
779 void bind_to(Label* L, int pos); | |
780 void link_to(Label* L, Label* appendix); | |
781 void next(Label* L); | |
782 | |
783 // Record reloc info for current pc_ | |
784 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0); | |
785 }; | |
786 | |
787 } } // namespace v8::internal | |
788 | |
789 #endif // V8_ASSEMBLER_ARM_H_ | |
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