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| 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | |
| 2 // All Rights Reserved. | |
| 3 // | |
| 4 // Redistribution and use in source and binary forms, with or without | |
| 5 // modification, are permitted provided that the following conditions | |
| 6 // are met: | |
| 7 // | |
| 8 // - Redistributions of source code must retain the above copyright notice, | |
| 9 // this list of conditions and the following disclaimer. | |
| 10 // | |
| 11 // - Redistribution in binary form must reproduce the above copyright | |
| 12 // notice, this list of conditions and the following disclaimer in the | |
| 13 // documentation and/or other materials provided with the | |
| 14 // distribution. | |
| 15 // | |
| 16 // - Neither the name of Sun Microsystems or the names of contributors may | |
| 17 // be used to endorse or promote products derived from this software without | |
| 18 // specific prior written permission. | |
| 19 // | |
| 20 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
| 21 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
| 22 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS | |
| 23 // FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE | |
| 24 // COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, | |
| 25 // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
| 26 // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
| 27 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
| 28 // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, | |
| 29 // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
| 30 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED | |
| 31 // OF THE POSSIBILITY OF SUCH DAMAGE. | |
| 32 | |
| 33 // The original source code covered by the above license above has been modified | |
| 34 // significantly by Google Inc. | |
| 35 // Copyright 2006-2008 the V8 project authors. All rights reserved. | |
| 36 | |
| 37 #include "v8.h" | |
| 38 | |
| 39 #include "assembler-arm-inl.h" | |
| 40 #include "serialize.h" | |
| 41 | |
| 42 namespace v8 { namespace internal { | |
| 43 | |
| 44 // ----------------------------------------------------------------------------- | |
| 45 // Implementation of Register and CRegister | |
| 46 | |
| 47 Register no_reg = { -1 }; | |
| 48 | |
| 49 Register r0 = { 0 }; | |
| 50 Register r1 = { 1 }; | |
| 51 Register r2 = { 2 }; | |
| 52 Register r3 = { 3 }; | |
| 53 Register r4 = { 4 }; | |
| 54 Register r5 = { 5 }; | |
| 55 Register r6 = { 6 }; | |
| 56 Register r7 = { 7 }; | |
| 57 Register r8 = { 8 }; | |
| 58 Register r9 = { 9 }; | |
| 59 Register r10 = { 10 }; | |
| 60 Register fp = { 11 }; | |
| 61 Register ip = { 12 }; | |
| 62 Register sp = { 13 }; | |
| 63 Register lr = { 14 }; | |
| 64 Register pc = { 15 }; | |
| 65 | |
| 66 | |
| 67 CRegister no_creg = { -1 }; | |
| 68 | |
| 69 CRegister cr0 = { 0 }; | |
| 70 CRegister cr1 = { 1 }; | |
| 71 CRegister cr2 = { 2 }; | |
| 72 CRegister cr3 = { 3 }; | |
| 73 CRegister cr4 = { 4 }; | |
| 74 CRegister cr5 = { 5 }; | |
| 75 CRegister cr6 = { 6 }; | |
| 76 CRegister cr7 = { 7 }; | |
| 77 CRegister cr8 = { 8 }; | |
| 78 CRegister cr9 = { 9 }; | |
| 79 CRegister cr10 = { 10 }; | |
| 80 CRegister cr11 = { 11 }; | |
| 81 CRegister cr12 = { 12 }; | |
| 82 CRegister cr13 = { 13 }; | |
| 83 CRegister cr14 = { 14 }; | |
| 84 CRegister cr15 = { 15 }; | |
| 85 | |
| 86 | |
| 87 // ----------------------------------------------------------------------------- | |
| 88 // Implementation of RelocInfo | |
| 89 | |
| 90 const int RelocInfo::kApplyMask = 0; | |
| 91 | |
| 92 | |
| 93 void RelocInfo::PatchCode(byte* instructions, int instruction_count) { | |
| 94 // Patch the code at the current address with the supplied instructions. | |
| 95 UNIMPLEMENTED(); | |
| 96 } | |
| 97 | |
| 98 | |
| 99 // Patch the code at the current PC with a call to the target address. | |
| 100 // Additional guard instructions can be added if required. | |
| 101 void RelocInfo::PatchCodeWithCall(Address target, int guard_bytes) { | |
| 102 // Patch the code at the current address with a call to the target. | |
| 103 UNIMPLEMENTED(); | |
| 104 } | |
| 105 | |
| 106 | |
| 107 // ----------------------------------------------------------------------------- | |
| 108 // Implementation of Operand and MemOperand | |
| 109 // See assembler-arm-inl.h for inlined constructors | |
| 110 | |
| 111 Operand::Operand(Handle<Object> handle) { | |
| 112 rm_ = no_reg; | |
| 113 // Verify all Objects referred by code are NOT in new space. | |
| 114 Object* obj = *handle; | |
| 115 ASSERT(!Heap::InNewSpace(obj)); | |
| 116 if (obj->IsHeapObject()) { | |
| 117 imm32_ = reinterpret_cast<intptr_t>(handle.location()); | |
| 118 rmode_ = RelocInfo::EMBEDDED_OBJECT; | |
| 119 } else { | |
| 120 // no relocation needed | |
| 121 imm32_ = reinterpret_cast<intptr_t>(obj); | |
| 122 rmode_ = RelocInfo::NONE; | |
| 123 } | |
| 124 } | |
| 125 | |
| 126 | |
| 127 Operand::Operand(Register rm, ShiftOp shift_op, int shift_imm) { | |
| 128 ASSERT(is_uint5(shift_imm)); | |
| 129 ASSERT(shift_op != ROR || shift_imm != 0); // use RRX if you mean it | |
| 130 rm_ = rm; | |
| 131 rs_ = no_reg; | |
| 132 shift_op_ = shift_op; | |
| 133 shift_imm_ = shift_imm & 31; | |
| 134 if (shift_op == RRX) { | |
| 135 // encoded as ROR with shift_imm == 0 | |
| 136 ASSERT(shift_imm == 0); | |
| 137 shift_op_ = ROR; | |
| 138 shift_imm_ = 0; | |
| 139 } | |
| 140 } | |
| 141 | |
| 142 | |
| 143 Operand::Operand(Register rm, ShiftOp shift_op, Register rs) { | |
| 144 ASSERT(shift_op != RRX); | |
| 145 rm_ = rm; | |
| 146 rs_ = no_reg; | |
| 147 shift_op_ = shift_op; | |
| 148 rs_ = rs; | |
| 149 } | |
| 150 | |
| 151 | |
| 152 MemOperand::MemOperand(Register rn, int32_t offset, AddrMode am) { | |
| 153 rn_ = rn; | |
| 154 rm_ = no_reg; | |
| 155 offset_ = offset; | |
| 156 am_ = am; | |
| 157 } | |
| 158 | |
| 159 MemOperand::MemOperand(Register rn, Register rm, AddrMode am) { | |
| 160 rn_ = rn; | |
| 161 rm_ = rm; | |
| 162 shift_op_ = LSL; | |
| 163 shift_imm_ = 0; | |
| 164 am_ = am; | |
| 165 } | |
| 166 | |
| 167 | |
| 168 MemOperand::MemOperand(Register rn, Register rm, | |
| 169 ShiftOp shift_op, int shift_imm, AddrMode am) { | |
| 170 ASSERT(is_uint5(shift_imm)); | |
| 171 rn_ = rn; | |
| 172 rm_ = rm; | |
| 173 shift_op_ = shift_op; | |
| 174 shift_imm_ = shift_imm & 31; | |
| 175 am_ = am; | |
| 176 } | |
| 177 | |
| 178 | |
| 179 // ----------------------------------------------------------------------------- | |
| 180 // Implementation of Assembler | |
| 181 | |
| 182 // Instruction encoding bits | |
| 183 enum { | |
| 184 H = 1 << 5, // halfword (or byte) | |
| 185 S6 = 1 << 6, // signed (or unsigned) | |
| 186 L = 1 << 20, // load (or store) | |
| 187 S = 1 << 20, // set condition code (or leave unchanged) | |
| 188 W = 1 << 21, // writeback base register (or leave unchanged) | |
| 189 A = 1 << 21, // accumulate in multiply instruction (or not) | |
| 190 B = 1 << 22, // unsigned byte (or word) | |
| 191 N = 1 << 22, // long (or short) | |
| 192 U = 1 << 23, // positive (or negative) offset/index | |
| 193 P = 1 << 24, // offset/pre-indexed addressing (or post-indexed addressing) | |
| 194 I = 1 << 25, // immediate shifter operand (or not) | |
| 195 | |
| 196 B4 = 1 << 4, | |
| 197 B5 = 1 << 5, | |
| 198 B7 = 1 << 7, | |
| 199 B8 = 1 << 8, | |
| 200 B12 = 1 << 12, | |
| 201 B16 = 1 << 16, | |
| 202 B20 = 1 << 20, | |
| 203 B21 = 1 << 21, | |
| 204 B22 = 1 << 22, | |
| 205 B23 = 1 << 23, | |
| 206 B24 = 1 << 24, | |
| 207 B25 = 1 << 25, | |
| 208 B26 = 1 << 26, | |
| 209 B27 = 1 << 27, | |
| 210 | |
| 211 // Instruction bit masks | |
| 212 RdMask = 15 << 12, // in str instruction | |
| 213 CondMask = 15 << 28, | |
| 214 OpCodeMask = 15 << 21, // in data-processing instructions | |
| 215 Imm24Mask = (1 << 24) - 1, | |
| 216 Off12Mask = (1 << 12) - 1, | |
| 217 // Reserved condition | |
| 218 nv = 15 << 28 | |
| 219 }; | |
| 220 | |
| 221 | |
| 222 // add(sp, sp, 4) instruction (aka Pop()) | |
| 223 static const Instr kPopInstruction = | |
| 224 al | 4 * B21 | 4 | LeaveCC | I | sp.code() * B16 | sp.code() * B12; | |
| 225 // str(r, MemOperand(sp, 4, NegPreIndex), al) instruction (aka push(r)) | |
| 226 // register r is not encoded. | |
| 227 static const Instr kPushRegPattern = | |
| 228 al | B26 | 4 | NegPreIndex | sp.code() * B16; | |
| 229 // ldr(r, MemOperand(sp, 4, PostIndex), al) instruction (aka pop(r)) | |
| 230 // register r is not encoded. | |
| 231 static const Instr kPopRegPattern = | |
| 232 al | B26 | L | 4 | PostIndex | sp.code() * B16; | |
| 233 | |
| 234 // spare_buffer_ | |
| 235 static const int kMinimalBufferSize = 4*KB; | |
| 236 static byte* spare_buffer_ = NULL; | |
| 237 | |
| 238 Assembler::Assembler(void* buffer, int buffer_size) { | |
| 239 if (buffer == NULL) { | |
| 240 // do our own buffer management | |
| 241 if (buffer_size <= kMinimalBufferSize) { | |
| 242 buffer_size = kMinimalBufferSize; | |
| 243 | |
| 244 if (spare_buffer_ != NULL) { | |
| 245 buffer = spare_buffer_; | |
| 246 spare_buffer_ = NULL; | |
| 247 } | |
| 248 } | |
| 249 if (buffer == NULL) { | |
| 250 buffer_ = NewArray<byte>(buffer_size); | |
| 251 } else { | |
| 252 buffer_ = static_cast<byte*>(buffer); | |
| 253 } | |
| 254 buffer_size_ = buffer_size; | |
| 255 own_buffer_ = true; | |
| 256 | |
| 257 } else { | |
| 258 // use externally provided buffer instead | |
| 259 ASSERT(buffer_size > 0); | |
| 260 buffer_ = static_cast<byte*>(buffer); | |
| 261 buffer_size_ = buffer_size; | |
| 262 own_buffer_ = false; | |
| 263 } | |
| 264 | |
| 265 // setup buffer pointers | |
| 266 ASSERT(buffer_ != NULL); | |
| 267 pc_ = buffer_; | |
| 268 reloc_info_writer.Reposition(buffer_ + buffer_size, pc_); | |
| 269 num_prinfo_ = 0; | |
| 270 next_buffer_check_ = 0; | |
| 271 no_const_pool_before_ = 0; | |
| 272 last_const_pool_end_ = 0; | |
| 273 last_bound_pos_ = 0; | |
| 274 current_statement_position_ = RelocInfo::kNoPosition; | |
| 275 current_position_ = RelocInfo::kNoPosition; | |
| 276 written_statement_position_ = current_statement_position_; | |
| 277 written_position_ = current_position_; | |
| 278 } | |
| 279 | |
| 280 | |
| 281 Assembler::~Assembler() { | |
| 282 if (own_buffer_) { | |
| 283 if (spare_buffer_ == NULL && buffer_size_ == kMinimalBufferSize) { | |
| 284 spare_buffer_ = buffer_; | |
| 285 } else { | |
| 286 DeleteArray(buffer_); | |
| 287 } | |
| 288 } | |
| 289 } | |
| 290 | |
| 291 | |
| 292 void Assembler::GetCode(CodeDesc* desc) { | |
| 293 // emit constant pool if necessary | |
| 294 CheckConstPool(true, false); | |
| 295 ASSERT(num_prinfo_ == 0); | |
| 296 | |
| 297 // setup desc | |
| 298 desc->buffer = buffer_; | |
| 299 desc->buffer_size = buffer_size_; | |
| 300 desc->instr_size = pc_offset(); | |
| 301 desc->reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos(); | |
| 302 } | |
| 303 | |
| 304 | |
| 305 void Assembler::Align(int m) { | |
| 306 ASSERT(m >= 4 && IsPowerOf2(m)); | |
| 307 while ((pc_offset() & (m - 1)) != 0) { | |
| 308 nop(); | |
| 309 } | |
| 310 } | |
| 311 | |
| 312 | |
| 313 // Labels refer to positions in the (to be) generated code. | |
| 314 // There are bound, linked, and unused labels. | |
| 315 // | |
| 316 // Bound labels refer to known positions in the already | |
| 317 // generated code. pos() is the position the label refers to. | |
| 318 // | |
| 319 // Linked labels refer to unknown positions in the code | |
| 320 // to be generated; pos() is the position of the last | |
| 321 // instruction using the label. | |
| 322 | |
| 323 | |
| 324 // The link chain is terminated by a negative code position (must be aligned) | |
| 325 const int kEndOfChain = -4; | |
| 326 | |
| 327 | |
| 328 int Assembler::target_at(int pos) { | |
| 329 Instr instr = instr_at(pos); | |
| 330 ASSERT((instr & 7*B25) == 5*B25); // b, bl, or blx imm24 | |
| 331 int imm26 = ((instr & Imm24Mask) << 8) >> 6; | |
| 332 if ((instr & CondMask) == nv && (instr & B24) != 0) | |
| 333 // blx uses bit 24 to encode bit 2 of imm26 | |
| 334 imm26 += 2; | |
| 335 | |
| 336 return pos + 8 + imm26; | |
| 337 } | |
| 338 | |
| 339 | |
| 340 void Assembler::target_at_put(int pos, int target_pos) { | |
| 341 int imm26 = target_pos - pos - 8; | |
| 342 Instr instr = instr_at(pos); | |
| 343 ASSERT((instr & 7*B25) == 5*B25); // b, bl, or blx imm24 | |
| 344 if ((instr & CondMask) == nv) { | |
| 345 // blx uses bit 24 to encode bit 2 of imm26 | |
| 346 ASSERT((imm26 & 1) == 0); | |
| 347 instr = (instr & ~(B24 | Imm24Mask)) | ((imm26 & 2) >> 1)*B24; | |
| 348 } else { | |
| 349 ASSERT((imm26 & 3) == 0); | |
| 350 instr &= ~Imm24Mask; | |
| 351 } | |
| 352 int imm24 = imm26 >> 2; | |
| 353 ASSERT(is_int24(imm24)); | |
| 354 instr_at_put(pos, instr | (imm24 & Imm24Mask)); | |
| 355 } | |
| 356 | |
| 357 | |
| 358 void Assembler::print(Label* L) { | |
| 359 if (L->is_unused()) { | |
| 360 PrintF("unused label\n"); | |
| 361 } else if (L->is_bound()) { | |
| 362 PrintF("bound label to %d\n", L->pos()); | |
| 363 } else if (L->is_linked()) { | |
| 364 Label l = *L; | |
| 365 PrintF("unbound label"); | |
| 366 while (l.is_linked()) { | |
| 367 PrintF("@ %d ", l.pos()); | |
| 368 Instr instr = instr_at(l.pos()); | |
| 369 ASSERT((instr & 7*B25) == 5*B25); // b, bl, or blx | |
| 370 int cond = instr & CondMask; | |
| 371 const char* b; | |
| 372 const char* c; | |
| 373 if (cond == nv) { | |
| 374 b = "blx"; | |
| 375 c = ""; | |
| 376 } else { | |
| 377 if ((instr & B24) != 0) | |
| 378 b = "bl"; | |
| 379 else | |
| 380 b = "b"; | |
| 381 | |
| 382 switch (cond) { | |
| 383 case eq: c = "eq"; break; | |
| 384 case ne: c = "ne"; break; | |
| 385 case hs: c = "hs"; break; | |
| 386 case lo: c = "lo"; break; | |
| 387 case mi: c = "mi"; break; | |
| 388 case pl: c = "pl"; break; | |
| 389 case vs: c = "vs"; break; | |
| 390 case vc: c = "vc"; break; | |
| 391 case hi: c = "hi"; break; | |
| 392 case ls: c = "ls"; break; | |
| 393 case ge: c = "ge"; break; | |
| 394 case lt: c = "lt"; break; | |
| 395 case gt: c = "gt"; break; | |
| 396 case le: c = "le"; break; | |
| 397 case al: c = ""; break; | |
| 398 default: | |
| 399 c = ""; | |
| 400 UNREACHABLE(); | |
| 401 } | |
| 402 } | |
| 403 PrintF("%s%s\n", b, c); | |
| 404 next(&l); | |
| 405 } | |
| 406 } else { | |
| 407 PrintF("label in inconsistent state (pos = %d)\n", L->pos_); | |
| 408 } | |
| 409 } | |
| 410 | |
| 411 | |
| 412 void Assembler::bind_to(Label* L, int pos) { | |
| 413 ASSERT(0 <= pos && pos <= pc_offset()); // must have a valid binding position | |
| 414 while (L->is_linked()) { | |
| 415 int fixup_pos = L->pos(); | |
| 416 next(L); // call next before overwriting link with target at fixup_pos | |
| 417 target_at_put(fixup_pos, pos); | |
| 418 } | |
| 419 L->bind_to(pos); | |
| 420 | |
| 421 // Keep track of the last bound label so we don't eliminate any instructions | |
| 422 // before a bound label. | |
| 423 if (pos > last_bound_pos_) | |
| 424 last_bound_pos_ = pos; | |
| 425 } | |
| 426 | |
| 427 | |
| 428 void Assembler::link_to(Label* L, Label* appendix) { | |
| 429 if (appendix->is_linked()) { | |
| 430 if (L->is_linked()) { | |
| 431 // append appendix to L's list | |
| 432 int fixup_pos; | |
| 433 int link = L->pos(); | |
| 434 do { | |
| 435 fixup_pos = link; | |
| 436 link = target_at(fixup_pos); | |
| 437 } while (link > 0); | |
| 438 ASSERT(link == kEndOfChain); | |
| 439 target_at_put(fixup_pos, appendix->pos()); | |
| 440 } else { | |
| 441 // L is empty, simply use appendix | |
| 442 *L = *appendix; | |
| 443 } | |
| 444 } | |
| 445 appendix->Unuse(); // appendix should not be used anymore | |
| 446 } | |
| 447 | |
| 448 | |
| 449 void Assembler::bind(Label* L) { | |
| 450 ASSERT(!L->is_bound()); // label can only be bound once | |
| 451 bind_to(L, pc_offset()); | |
| 452 } | |
| 453 | |
| 454 | |
| 455 void Assembler::next(Label* L) { | |
| 456 ASSERT(L->is_linked()); | |
| 457 int link = target_at(L->pos()); | |
| 458 if (link > 0) { | |
| 459 L->link_to(link); | |
| 460 } else { | |
| 461 ASSERT(link == kEndOfChain); | |
| 462 L->Unuse(); | |
| 463 } | |
| 464 } | |
| 465 | |
| 466 | |
| 467 // Low-level code emission routines depending on the addressing mode | |
| 468 static bool fits_shifter(uint32_t imm32, | |
| 469 uint32_t* rotate_imm, | |
| 470 uint32_t* immed_8, | |
| 471 Instr* instr) { | |
| 472 // imm32 must be unsigned | |
| 473 for (int rot = 0; rot < 16; rot++) { | |
| 474 uint32_t imm8 = (imm32 << 2*rot) | (imm32 >> (32 - 2*rot)); | |
| 475 if ((imm8 <= 0xff)) { | |
| 476 *rotate_imm = rot; | |
| 477 *immed_8 = imm8; | |
| 478 return true; | |
| 479 } | |
| 480 } | |
| 481 // if the opcode is mov or mvn and if ~imm32 fits, change the opcode | |
| 482 if (instr != NULL && (*instr & 0xd*B21) == 0xd*B21) { | |
| 483 if (fits_shifter(~imm32, rotate_imm, immed_8, NULL)) { | |
| 484 *instr ^= 0x2*B21; | |
| 485 return true; | |
| 486 } | |
| 487 } | |
| 488 return false; | |
| 489 } | |
| 490 | |
| 491 | |
| 492 void Assembler::addrmod1(Instr instr, | |
| 493 Register rn, | |
| 494 Register rd, | |
| 495 const Operand& x) { | |
| 496 CheckBuffer(); | |
| 497 ASSERT((instr & ~(CondMask | OpCodeMask | S)) == 0); | |
| 498 if (!x.rm_.is_valid()) { | |
| 499 // immediate | |
| 500 uint32_t rotate_imm; | |
| 501 uint32_t immed_8; | |
| 502 if ((x.rmode_ != RelocInfo::NONE && | |
| 503 x.rmode_ != RelocInfo::EXTERNAL_REFERENCE) || | |
| 504 !fits_shifter(x.imm32_, &rotate_imm, &immed_8, &instr)) { | |
| 505 // The immediate operand cannot be encoded as a shifter operand, so load | |
| 506 // it first to register ip and change the original instruction to use ip. | |
| 507 // However, if the original instruction is a 'mov rd, x' (not setting the | |
| 508 // condition code), then replace it with a 'ldr rd, [pc]' | |
| 509 RecordRelocInfo(x.rmode_, x.imm32_); | |
| 510 CHECK(!rn.is(ip)); // rn should never be ip, or will be trashed | |
| 511 Condition cond = static_cast<Condition>(instr & CondMask); | |
| 512 if ((instr & ~CondMask) == 13*B21) { // mov, S not set | |
| 513 ldr(rd, MemOperand(pc, 0), cond); | |
| 514 } else { | |
| 515 ldr(ip, MemOperand(pc, 0), cond); | |
| 516 addrmod1(instr, rn, rd, Operand(ip)); | |
| 517 } | |
| 518 return; | |
| 519 } | |
| 520 instr |= I | rotate_imm*B8 | immed_8; | |
| 521 } else if (!x.rs_.is_valid()) { | |
| 522 // immediate shift | |
| 523 instr |= x.shift_imm_*B7 | x.shift_op_ | x.rm_.code(); | |
| 524 } else { | |
| 525 // register shift | |
| 526 ASSERT(!rn.is(pc) && !rd.is(pc) && !x.rm_.is(pc) && !x.rs_.is(pc)); | |
| 527 instr |= x.rs_.code()*B8 | x.shift_op_ | B4 | x.rm_.code(); | |
| 528 } | |
| 529 emit(instr | rn.code()*B16 | rd.code()*B12); | |
| 530 if (rn.is(pc) || x.rm_.is(pc)) | |
| 531 // block constant pool emission for one instruction after reading pc | |
| 532 BlockConstPoolBefore(pc_offset() + kInstrSize); | |
| 533 } | |
| 534 | |
| 535 | |
| 536 void Assembler::addrmod2(Instr instr, Register rd, const MemOperand& x) { | |
| 537 ASSERT((instr & ~(CondMask | B | L)) == B26); | |
| 538 int am = x.am_; | |
| 539 if (!x.rm_.is_valid()) { | |
| 540 // immediate offset | |
| 541 int offset_12 = x.offset_; | |
| 542 if (offset_12 < 0) { | |
| 543 offset_12 = -offset_12; | |
| 544 am ^= U; | |
| 545 } | |
| 546 if (!is_uint12(offset_12)) { | |
| 547 // immediate offset cannot be encoded, load it first to register ip | |
| 548 // rn (and rd in a load) should never be ip, or will be trashed | |
| 549 ASSERT(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip))); | |
| 550 mov(ip, Operand(x.offset_), LeaveCC, | |
| 551 static_cast<Condition>(instr & CondMask)); | |
| 552 addrmod2(instr, rd, MemOperand(x.rn_, ip, x.am_)); | |
| 553 return; | |
| 554 } | |
| 555 ASSERT(offset_12 >= 0); // no masking needed | |
| 556 instr |= offset_12; | |
| 557 } else { | |
| 558 // register offset (shift_imm_ and shift_op_ are 0) or scaled | |
| 559 // register offset the constructors make sure than both shift_imm_ | |
| 560 // and shift_op_ are initialized | |
| 561 ASSERT(!x.rm_.is(pc)); | |
| 562 instr |= B25 | x.shift_imm_*B7 | x.shift_op_ | x.rm_.code(); | |
| 563 } | |
| 564 ASSERT((am & (P|W)) == P || !x.rn_.is(pc)); // no pc base with writeback | |
| 565 emit(instr | am | x.rn_.code()*B16 | rd.code()*B12); | |
| 566 } | |
| 567 | |
| 568 | |
| 569 void Assembler::addrmod3(Instr instr, Register rd, const MemOperand& x) { | |
| 570 ASSERT((instr & ~(CondMask | L | S6 | H)) == (B4 | B7)); | |
| 571 ASSERT(x.rn_.is_valid()); | |
| 572 int am = x.am_; | |
| 573 if (!x.rm_.is_valid()) { | |
| 574 // immediate offset | |
| 575 int offset_8 = x.offset_; | |
| 576 if (offset_8 < 0) { | |
| 577 offset_8 = -offset_8; | |
| 578 am ^= U; | |
| 579 } | |
| 580 if (!is_uint8(offset_8)) { | |
| 581 // immediate offset cannot be encoded, load it first to register ip | |
| 582 // rn (and rd in a load) should never be ip, or will be trashed | |
| 583 ASSERT(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip))); | |
| 584 mov(ip, Operand(x.offset_), LeaveCC, | |
| 585 static_cast<Condition>(instr & CondMask)); | |
| 586 addrmod3(instr, rd, MemOperand(x.rn_, ip, x.am_)); | |
| 587 return; | |
| 588 } | |
| 589 ASSERT(offset_8 >= 0); // no masking needed | |
| 590 instr |= B | (offset_8 >> 4)*B8 | (offset_8 & 0xf); | |
| 591 } else if (x.shift_imm_ != 0) { | |
| 592 // scaled register offset not supported, load index first | |
| 593 // rn (and rd in a load) should never be ip, or will be trashed | |
| 594 ASSERT(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip))); | |
| 595 mov(ip, Operand(x.rm_, x.shift_op_, x.shift_imm_), LeaveCC, | |
| 596 static_cast<Condition>(instr & CondMask)); | |
| 597 addrmod3(instr, rd, MemOperand(x.rn_, ip, x.am_)); | |
| 598 return; | |
| 599 } else { | |
| 600 // register offset | |
| 601 ASSERT((am & (P|W)) == P || !x.rm_.is(pc)); // no pc index with writeback | |
| 602 instr |= x.rm_.code(); | |
| 603 } | |
| 604 ASSERT((am & (P|W)) == P || !x.rn_.is(pc)); // no pc base with writeback | |
| 605 emit(instr | am | x.rn_.code()*B16 | rd.code()*B12); | |
| 606 } | |
| 607 | |
| 608 | |
| 609 void Assembler::addrmod4(Instr instr, Register rn, RegList rl) { | |
| 610 ASSERT((instr & ~(CondMask | P | U | W | L)) == B27); | |
| 611 ASSERT(rl != 0); | |
| 612 ASSERT(!rn.is(pc)); | |
| 613 emit(instr | rn.code()*B16 | rl); | |
| 614 } | |
| 615 | |
| 616 | |
| 617 void Assembler::addrmod5(Instr instr, CRegister crd, const MemOperand& x) { | |
| 618 // unindexed addressing is not encoded by this function | |
| 619 ASSERT((instr & ~(CondMask | P | U | N | W | L)) == (B27 | B26)); | |
| 620 ASSERT(x.rn_.is_valid() && !x.rm_.is_valid()); | |
| 621 int am = x.am_; | |
| 622 int offset_8 = x.offset_; | |
| 623 ASSERT((offset_8 & 3) == 0); // offset must be an aligned word offset | |
| 624 offset_8 >>= 2; | |
| 625 if (offset_8 < 0) { | |
| 626 offset_8 = -offset_8; | |
| 627 am ^= U; | |
| 628 } | |
| 629 ASSERT(is_uint8(offset_8)); // unsigned word offset must fit in a byte | |
| 630 ASSERT((am & (P|W)) == P || !x.rn_.is(pc)); // no pc base with writeback | |
| 631 | |
| 632 // post-indexed addressing requires W == 1; different than in addrmod2/3 | |
| 633 if ((am & P) == 0) | |
| 634 am |= W; | |
| 635 | |
| 636 ASSERT(offset_8 >= 0); // no masking needed | |
| 637 emit(instr | am | x.rn_.code()*B16 | crd.code()*B12 | offset_8); | |
| 638 } | |
| 639 | |
| 640 | |
| 641 int Assembler::branch_offset(Label* L, bool jump_elimination_allowed) { | |
| 642 int target_pos; | |
| 643 if (L->is_bound()) { | |
| 644 target_pos = L->pos(); | |
| 645 } else { | |
| 646 if (L->is_linked()) { | |
| 647 target_pos = L->pos(); // L's link | |
| 648 } else { | |
| 649 target_pos = kEndOfChain; | |
| 650 } | |
| 651 L->link_to(pc_offset()); | |
| 652 } | |
| 653 | |
| 654 // Block the emission of the constant pool, since the branch instruction must | |
| 655 // be emitted at the pc offset recorded by the label | |
| 656 BlockConstPoolBefore(pc_offset() + kInstrSize); | |
| 657 | |
| 658 return target_pos - pc_offset() - 8; | |
| 659 } | |
| 660 | |
| 661 | |
| 662 // Branch instructions | |
| 663 void Assembler::b(int branch_offset, Condition cond) { | |
| 664 ASSERT((branch_offset & 3) == 0); | |
| 665 int imm24 = branch_offset >> 2; | |
| 666 ASSERT(is_int24(imm24)); | |
| 667 emit(cond | B27 | B25 | (imm24 & Imm24Mask)); | |
| 668 | |
| 669 if (cond == al) | |
| 670 // dead code is a good location to emit the constant pool | |
| 671 CheckConstPool(false, false); | |
| 672 } | |
| 673 | |
| 674 | |
| 675 void Assembler::bl(int branch_offset, Condition cond) { | |
| 676 ASSERT((branch_offset & 3) == 0); | |
| 677 int imm24 = branch_offset >> 2; | |
| 678 ASSERT(is_int24(imm24)); | |
| 679 emit(cond | B27 | B25 | B24 | (imm24 & Imm24Mask)); | |
| 680 } | |
| 681 | |
| 682 | |
| 683 void Assembler::blx(int branch_offset) { // v5 and above | |
| 684 ASSERT((branch_offset & 1) == 0); | |
| 685 int h = ((branch_offset & 2) >> 1)*B24; | |
| 686 int imm24 = branch_offset >> 2; | |
| 687 ASSERT(is_int24(imm24)); | |
| 688 emit(15 << 28 | B27 | B25 | h | (imm24 & Imm24Mask)); | |
| 689 } | |
| 690 | |
| 691 | |
| 692 void Assembler::blx(Register target, Condition cond) { // v5 and above | |
| 693 ASSERT(!target.is(pc)); | |
| 694 emit(cond | B24 | B21 | 15*B16 | 15*B12 | 15*B8 | 3*B4 | target.code()); | |
| 695 } | |
| 696 | |
| 697 | |
| 698 void Assembler::bx(Register target, Condition cond) { // v5 and above, plus v4t | |
| 699 ASSERT(!target.is(pc)); // use of pc is actually allowed, but discouraged | |
| 700 emit(cond | B24 | B21 | 15*B16 | 15*B12 | 15*B8 | B4 | target.code()); | |
| 701 } | |
| 702 | |
| 703 | |
| 704 // Data-processing instructions | |
| 705 void Assembler::and_(Register dst, Register src1, const Operand& src2, | |
| 706 SBit s, Condition cond) { | |
| 707 addrmod1(cond | 0*B21 | s, src1, dst, src2); | |
| 708 } | |
| 709 | |
| 710 | |
| 711 void Assembler::eor(Register dst, Register src1, const Operand& src2, | |
| 712 SBit s, Condition cond) { | |
| 713 addrmod1(cond | 1*B21 | s, src1, dst, src2); | |
| 714 } | |
| 715 | |
| 716 | |
| 717 void Assembler::sub(Register dst, Register src1, const Operand& src2, | |
| 718 SBit s, Condition cond) { | |
| 719 addrmod1(cond | 2*B21 | s, src1, dst, src2); | |
| 720 } | |
| 721 | |
| 722 | |
| 723 void Assembler::rsb(Register dst, Register src1, const Operand& src2, | |
| 724 SBit s, Condition cond) { | |
| 725 addrmod1(cond | 3*B21 | s, src1, dst, src2); | |
| 726 } | |
| 727 | |
| 728 | |
| 729 void Assembler::add(Register dst, Register src1, const Operand& src2, | |
| 730 SBit s, Condition cond) { | |
| 731 addrmod1(cond | 4*B21 | s, src1, dst, src2); | |
| 732 | |
| 733 // Eliminate pattern: push(r), pop() | |
| 734 // str(src, MemOperand(sp, 4, NegPreIndex), al); | |
| 735 // add(sp, sp, Operand(kPointerSize)); | |
| 736 // Both instructions can be eliminated. | |
| 737 int pattern_size = 2 * kInstrSize; | |
| 738 if (FLAG_push_pop_elimination && | |
| 739 last_bound_pos_ <= (pc_offset() - pattern_size) && | |
| 740 reloc_info_writer.last_pc() <= (pc_ - pattern_size) && | |
| 741 // pattern | |
| 742 instr_at(pc_ - 1 * kInstrSize) == kPopInstruction && | |
| 743 (instr_at(pc_ - 2 * kInstrSize) & ~RdMask) == kPushRegPattern) { | |
| 744 pc_ -= 2 * kInstrSize; | |
| 745 if (FLAG_print_push_pop_elimination) { | |
| 746 PrintF("%x push(reg)/pop() eliminated\n", pc_offset()); | |
| 747 } | |
| 748 } | |
| 749 } | |
| 750 | |
| 751 | |
| 752 void Assembler::adc(Register dst, Register src1, const Operand& src2, | |
| 753 SBit s, Condition cond) { | |
| 754 addrmod1(cond | 5*B21 | s, src1, dst, src2); | |
| 755 } | |
| 756 | |
| 757 | |
| 758 void Assembler::sbc(Register dst, Register src1, const Operand& src2, | |
| 759 SBit s, Condition cond) { | |
| 760 addrmod1(cond | 6*B21 | s, src1, dst, src2); | |
| 761 } | |
| 762 | |
| 763 | |
| 764 void Assembler::rsc(Register dst, Register src1, const Operand& src2, | |
| 765 SBit s, Condition cond) { | |
| 766 addrmod1(cond | 7*B21 | s, src1, dst, src2); | |
| 767 } | |
| 768 | |
| 769 | |
| 770 void Assembler::tst(Register src1, const Operand& src2, Condition cond) { | |
| 771 addrmod1(cond | 8*B21 | S, src1, r0, src2); | |
| 772 } | |
| 773 | |
| 774 | |
| 775 void Assembler::teq(Register src1, const Operand& src2, Condition cond) { | |
| 776 addrmod1(cond | 9*B21 | S, src1, r0, src2); | |
| 777 } | |
| 778 | |
| 779 | |
| 780 void Assembler::cmp(Register src1, const Operand& src2, Condition cond) { | |
| 781 addrmod1(cond | 10*B21 | S, src1, r0, src2); | |
| 782 } | |
| 783 | |
| 784 | |
| 785 void Assembler::cmn(Register src1, const Operand& src2, Condition cond) { | |
| 786 addrmod1(cond | 11*B21 | S, src1, r0, src2); | |
| 787 } | |
| 788 | |
| 789 | |
| 790 void Assembler::orr(Register dst, Register src1, const Operand& src2, | |
| 791 SBit s, Condition cond) { | |
| 792 addrmod1(cond | 12*B21 | s, src1, dst, src2); | |
| 793 } | |
| 794 | |
| 795 | |
| 796 void Assembler::mov(Register dst, const Operand& src, SBit s, Condition cond) { | |
| 797 addrmod1(cond | 13*B21 | s, r0, dst, src); | |
| 798 } | |
| 799 | |
| 800 | |
| 801 void Assembler::bic(Register dst, Register src1, const Operand& src2, | |
| 802 SBit s, Condition cond) { | |
| 803 addrmod1(cond | 14*B21 | s, src1, dst, src2); | |
| 804 } | |
| 805 | |
| 806 | |
| 807 void Assembler::mvn(Register dst, const Operand& src, SBit s, Condition cond) { | |
| 808 addrmod1(cond | 15*B21 | s, r0, dst, src); | |
| 809 } | |
| 810 | |
| 811 | |
| 812 // Multiply instructions | |
| 813 void Assembler::mla(Register dst, Register src1, Register src2, Register srcA, | |
| 814 SBit s, Condition cond) { | |
| 815 ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc)); | |
| 816 ASSERT(!dst.is(src1)); | |
| 817 emit(cond | A | s | dst.code()*B16 | srcA.code()*B12 | | |
| 818 src2.code()*B8 | B7 | B4 | src1.code()); | |
| 819 } | |
| 820 | |
| 821 | |
| 822 void Assembler::mul(Register dst, Register src1, Register src2, | |
| 823 SBit s, Condition cond) { | |
| 824 ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc)); | |
| 825 ASSERT(!dst.is(src1)); | |
| 826 emit(cond | s | dst.code()*B16 | src2.code()*B8 | B7 | B4 | src1.code()); | |
| 827 } | |
| 828 | |
| 829 | |
| 830 void Assembler::smlal(Register dstL, | |
| 831 Register dstH, | |
| 832 Register src1, | |
| 833 Register src2, | |
| 834 SBit s, | |
| 835 Condition cond) { | |
| 836 ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc)); | |
| 837 ASSERT(!dstL.is(dstH) && !dstH.is(src1) && !src1.is(dstL)); | |
| 838 emit(cond | B23 | B22 | A | s | dstH.code()*B16 | dstL.code()*B12 | | |
| 839 src2.code()*B8 | B7 | B4 | src1.code()); | |
| 840 } | |
| 841 | |
| 842 | |
| 843 void Assembler::smull(Register dstL, | |
| 844 Register dstH, | |
| 845 Register src1, | |
| 846 Register src2, | |
| 847 SBit s, | |
| 848 Condition cond) { | |
| 849 ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc)); | |
| 850 ASSERT(!dstL.is(dstH) && !dstH.is(src1) && !src1.is(dstL)); | |
| 851 emit(cond | B23 | B22 | s | dstH.code()*B16 | dstL.code()*B12 | | |
| 852 src2.code()*B8 | B7 | B4 | src1.code()); | |
| 853 } | |
| 854 | |
| 855 | |
| 856 void Assembler::umlal(Register dstL, | |
| 857 Register dstH, | |
| 858 Register src1, | |
| 859 Register src2, | |
| 860 SBit s, | |
| 861 Condition cond) { | |
| 862 ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc)); | |
| 863 ASSERT(!dstL.is(dstH) && !dstH.is(src1) && !src1.is(dstL)); | |
| 864 emit(cond | B23 | A | s | dstH.code()*B16 | dstL.code()*B12 | | |
| 865 src2.code()*B8 | B7 | B4 | src1.code()); | |
| 866 } | |
| 867 | |
| 868 | |
| 869 void Assembler::umull(Register dstL, | |
| 870 Register dstH, | |
| 871 Register src1, | |
| 872 Register src2, | |
| 873 SBit s, | |
| 874 Condition cond) { | |
| 875 ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc)); | |
| 876 ASSERT(!dstL.is(dstH) && !dstH.is(src1) && !src1.is(dstL)); | |
| 877 emit(cond | B23 | s | dstH.code()*B16 | dstL.code()*B12 | | |
| 878 src2.code()*B8 | B7 | B4 | src1.code()); | |
| 879 } | |
| 880 | |
| 881 | |
| 882 // Miscellaneous arithmetic instructions | |
| 883 void Assembler::clz(Register dst, Register src, Condition cond) { | |
| 884 // v5 and above. | |
| 885 ASSERT(!dst.is(pc) && !src.is(pc)); | |
| 886 emit(cond | B24 | B22 | B21 | 15*B16 | dst.code()*B12 | | |
| 887 15*B8 | B4 | src.code()); | |
| 888 } | |
| 889 | |
| 890 | |
| 891 // Status register access instructions | |
| 892 void Assembler::mrs(Register dst, SRegister s, Condition cond) { | |
| 893 ASSERT(!dst.is(pc)); | |
| 894 emit(cond | B24 | s | 15*B16 | dst.code()*B12); | |
| 895 } | |
| 896 | |
| 897 | |
| 898 void Assembler::msr(SRegisterFieldMask fields, const Operand& src, | |
| 899 Condition cond) { | |
| 900 ASSERT(fields >= B16 && fields < B20); // at least one field set | |
| 901 Instr instr; | |
| 902 if (!src.rm_.is_valid()) { | |
| 903 // immediate | |
| 904 uint32_t rotate_imm; | |
| 905 uint32_t immed_8; | |
| 906 if ((src.rmode_ != RelocInfo::NONE && | |
| 907 src.rmode_ != RelocInfo::EXTERNAL_REFERENCE)|| | |
| 908 !fits_shifter(src.imm32_, &rotate_imm, &immed_8, NULL)) { | |
| 909 // immediate operand cannot be encoded, load it first to register ip | |
| 910 RecordRelocInfo(src.rmode_, src.imm32_); | |
| 911 ldr(ip, MemOperand(pc, 0), cond); | |
| 912 msr(fields, Operand(ip), cond); | |
| 913 return; | |
| 914 } | |
| 915 instr = I | rotate_imm*B8 | immed_8; | |
| 916 } else { | |
| 917 ASSERT(!src.rs_.is_valid() && src.shift_imm_ == 0); // only rm allowed | |
| 918 instr = src.rm_.code(); | |
| 919 } | |
| 920 emit(cond | instr | B24 | B21 | fields | 15*B12); | |
| 921 } | |
| 922 | |
| 923 | |
| 924 // Load/Store instructions | |
| 925 void Assembler::ldr(Register dst, const MemOperand& src, Condition cond) { | |
| 926 addrmod2(cond | B26 | L, dst, src); | |
| 927 | |
| 928 // Eliminate pattern: push(r), pop(r) | |
| 929 // str(r, MemOperand(sp, 4, NegPreIndex), al) | |
| 930 // ldr(r, MemOperand(sp, 4, PostIndex), al) | |
| 931 // Both instructions can be eliminated. | |
| 932 int pattern_size = 2 * kInstrSize; | |
| 933 if (FLAG_push_pop_elimination && | |
| 934 last_bound_pos_ <= (pc_offset() - pattern_size) && | |
| 935 reloc_info_writer.last_pc() <= (pc_ - pattern_size) && | |
| 936 // pattern | |
| 937 instr_at(pc_ - 1 * kInstrSize) == (kPopRegPattern | dst.code() * B12) && | |
| 938 instr_at(pc_ - 2 * kInstrSize) == (kPushRegPattern | dst.code() * B12)) { | |
| 939 pc_ -= 2 * kInstrSize; | |
| 940 if (FLAG_print_push_pop_elimination) { | |
| 941 PrintF("%x push/pop (same reg) eliminated\n", pc_offset()); | |
| 942 } | |
| 943 } | |
| 944 } | |
| 945 | |
| 946 | |
| 947 void Assembler::str(Register src, const MemOperand& dst, Condition cond) { | |
| 948 addrmod2(cond | B26, src, dst); | |
| 949 | |
| 950 // Eliminate pattern: pop(), push(r) | |
| 951 // add sp, sp, #4 LeaveCC, al; str r, [sp, #-4], al | |
| 952 // -> str r, [sp, 0], al | |
| 953 int pattern_size = 2 * kInstrSize; | |
| 954 if (FLAG_push_pop_elimination && | |
| 955 last_bound_pos_ <= (pc_offset() - pattern_size) && | |
| 956 reloc_info_writer.last_pc() <= (pc_ - pattern_size) && | |
| 957 instr_at(pc_ - 1 * kInstrSize) == (kPushRegPattern | src.code() * B12) && | |
| 958 instr_at(pc_ - 2 * kInstrSize) == kPopInstruction) { | |
| 959 pc_ -= 2 * kInstrSize; | |
| 960 emit(al | B26 | 0 | Offset | sp.code() * B16 | src.code() * B12); | |
| 961 if (FLAG_print_push_pop_elimination) { | |
| 962 PrintF("%x pop()/push(reg) eliminated\n", pc_offset()); | |
| 963 } | |
| 964 } | |
| 965 } | |
| 966 | |
| 967 | |
| 968 void Assembler::ldrb(Register dst, const MemOperand& src, Condition cond) { | |
| 969 addrmod2(cond | B26 | B | L, dst, src); | |
| 970 } | |
| 971 | |
| 972 | |
| 973 void Assembler::strb(Register src, const MemOperand& dst, Condition cond) { | |
| 974 addrmod2(cond | B26 | B, src, dst); | |
| 975 } | |
| 976 | |
| 977 | |
| 978 void Assembler::ldrh(Register dst, const MemOperand& src, Condition cond) { | |
| 979 addrmod3(cond | L | B7 | H | B4, dst, src); | |
| 980 } | |
| 981 | |
| 982 | |
| 983 void Assembler::strh(Register src, const MemOperand& dst, Condition cond) { | |
| 984 addrmod3(cond | B7 | H | B4, src, dst); | |
| 985 } | |
| 986 | |
| 987 | |
| 988 void Assembler::ldrsb(Register dst, const MemOperand& src, Condition cond) { | |
| 989 addrmod3(cond | L | B7 | S6 | B4, dst, src); | |
| 990 } | |
| 991 | |
| 992 | |
| 993 void Assembler::ldrsh(Register dst, const MemOperand& src, Condition cond) { | |
| 994 addrmod3(cond | L | B7 | S6 | H | B4, dst, src); | |
| 995 } | |
| 996 | |
| 997 | |
| 998 // Load/Store multiple instructions | |
| 999 void Assembler::ldm(BlockAddrMode am, | |
| 1000 Register base, | |
| 1001 RegList dst, | |
| 1002 Condition cond) { | |
| 1003 // ABI stack constraint: ldmxx base, {..sp..} base != sp is not restartable | |
| 1004 ASSERT(base.is(sp) || (dst & sp.bit()) == 0); | |
| 1005 | |
| 1006 addrmod4(cond | B27 | am | L, base, dst); | |
| 1007 | |
| 1008 // emit the constant pool after a function return implemented by ldm ..{..pc} | |
| 1009 if (cond == al && (dst & pc.bit()) != 0) { | |
| 1010 // There is a slight chance that the ldm instruction was actually a call, | |
| 1011 // in which case it would be wrong to return into the constant pool; we | |
| 1012 // recognize this case by checking if the emission of the pool was blocked | |
| 1013 // at the pc of the ldm instruction by a mov lr, pc instruction; if this is | |
| 1014 // the case, we emit a jump over the pool. | |
| 1015 CheckConstPool(true, no_const_pool_before_ == pc_offset() - kInstrSize); | |
| 1016 } | |
| 1017 } | |
| 1018 | |
| 1019 | |
| 1020 void Assembler::stm(BlockAddrMode am, | |
| 1021 Register base, | |
| 1022 RegList src, | |
| 1023 Condition cond) { | |
| 1024 addrmod4(cond | B27 | am, base, src); | |
| 1025 } | |
| 1026 | |
| 1027 | |
| 1028 // Semaphore instructions | |
| 1029 void Assembler::swp(Register dst, Register src, Register base, Condition cond) { | |
| 1030 ASSERT(!dst.is(pc) && !src.is(pc) && !base.is(pc)); | |
| 1031 ASSERT(!dst.is(base) && !src.is(base)); | |
| 1032 emit(cond | P | base.code()*B16 | dst.code()*B12 | | |
| 1033 B7 | B4 | src.code()); | |
| 1034 } | |
| 1035 | |
| 1036 | |
| 1037 void Assembler::swpb(Register dst, | |
| 1038 Register src, | |
| 1039 Register base, | |
| 1040 Condition cond) { | |
| 1041 ASSERT(!dst.is(pc) && !src.is(pc) && !base.is(pc)); | |
| 1042 ASSERT(!dst.is(base) && !src.is(base)); | |
| 1043 emit(cond | P | B | base.code()*B16 | dst.code()*B12 | | |
| 1044 B7 | B4 | src.code()); | |
| 1045 } | |
| 1046 | |
| 1047 | |
| 1048 // Exception-generating instructions and debugging support | |
| 1049 void Assembler::stop(const char* msg) { | |
| 1050 #if !defined(__arm__) | |
| 1051 // The simulator handles these special instructions and stops execution. | |
| 1052 emit(15 << 28 | ((intptr_t) msg)); | |
| 1053 #else | |
| 1054 // Just issue a simple break instruction for now. Alternatively we could use | |
| 1055 // the swi(0x9f0001) instruction on Linux. | |
| 1056 bkpt(0); | |
| 1057 #endif | |
| 1058 } | |
| 1059 | |
| 1060 | |
| 1061 void Assembler::bkpt(uint32_t imm16) { // v5 and above | |
| 1062 ASSERT(is_uint16(imm16)); | |
| 1063 emit(al | B24 | B21 | (imm16 >> 4)*B8 | 7*B4 | (imm16 & 0xf)); | |
| 1064 } | |
| 1065 | |
| 1066 | |
| 1067 void Assembler::swi(uint32_t imm24, Condition cond) { | |
| 1068 ASSERT(is_uint24(imm24)); | |
| 1069 emit(cond | 15*B24 | imm24); | |
| 1070 } | |
| 1071 | |
| 1072 | |
| 1073 // Coprocessor instructions | |
| 1074 void Assembler::cdp(Coprocessor coproc, | |
| 1075 int opcode_1, | |
| 1076 CRegister crd, | |
| 1077 CRegister crn, | |
| 1078 CRegister crm, | |
| 1079 int opcode_2, | |
| 1080 Condition cond) { | |
| 1081 ASSERT(is_uint4(opcode_1) && is_uint3(opcode_2)); | |
| 1082 emit(cond | B27 | B26 | B25 | (opcode_1 & 15)*B20 | crn.code()*B16 | | |
| 1083 crd.code()*B12 | coproc*B8 | (opcode_2 & 7)*B5 | crm.code()); | |
| 1084 } | |
| 1085 | |
| 1086 | |
| 1087 void Assembler::cdp2(Coprocessor coproc, | |
| 1088 int opcode_1, | |
| 1089 CRegister crd, | |
| 1090 CRegister crn, | |
| 1091 CRegister crm, | |
| 1092 int opcode_2) { // v5 and above | |
| 1093 cdp(coproc, opcode_1, crd, crn, crm, opcode_2, static_cast<Condition>(nv)); | |
| 1094 } | |
| 1095 | |
| 1096 | |
| 1097 void Assembler::mcr(Coprocessor coproc, | |
| 1098 int opcode_1, | |
| 1099 Register rd, | |
| 1100 CRegister crn, | |
| 1101 CRegister crm, | |
| 1102 int opcode_2, | |
| 1103 Condition cond) { | |
| 1104 ASSERT(is_uint3(opcode_1) && is_uint3(opcode_2)); | |
| 1105 emit(cond | B27 | B26 | B25 | (opcode_1 & 7)*B21 | crn.code()*B16 | | |
| 1106 rd.code()*B12 | coproc*B8 | (opcode_2 & 7)*B5 | B4 | crm.code()); | |
| 1107 } | |
| 1108 | |
| 1109 | |
| 1110 void Assembler::mcr2(Coprocessor coproc, | |
| 1111 int opcode_1, | |
| 1112 Register rd, | |
| 1113 CRegister crn, | |
| 1114 CRegister crm, | |
| 1115 int opcode_2) { // v5 and above | |
| 1116 mcr(coproc, opcode_1, rd, crn, crm, opcode_2, static_cast<Condition>(nv)); | |
| 1117 } | |
| 1118 | |
| 1119 | |
| 1120 void Assembler::mrc(Coprocessor coproc, | |
| 1121 int opcode_1, | |
| 1122 Register rd, | |
| 1123 CRegister crn, | |
| 1124 CRegister crm, | |
| 1125 int opcode_2, | |
| 1126 Condition cond) { | |
| 1127 ASSERT(is_uint3(opcode_1) && is_uint3(opcode_2)); | |
| 1128 emit(cond | B27 | B26 | B25 | (opcode_1 & 7)*B21 | L | crn.code()*B16 | | |
| 1129 rd.code()*B12 | coproc*B8 | (opcode_2 & 7)*B5 | B4 | crm.code()); | |
| 1130 } | |
| 1131 | |
| 1132 | |
| 1133 void Assembler::mrc2(Coprocessor coproc, | |
| 1134 int opcode_1, | |
| 1135 Register rd, | |
| 1136 CRegister crn, | |
| 1137 CRegister crm, | |
| 1138 int opcode_2) { // v5 and above | |
| 1139 mrc(coproc, opcode_1, rd, crn, crm, opcode_2, static_cast<Condition>(nv)); | |
| 1140 } | |
| 1141 | |
| 1142 | |
| 1143 void Assembler::ldc(Coprocessor coproc, | |
| 1144 CRegister crd, | |
| 1145 const MemOperand& src, | |
| 1146 LFlag l, | |
| 1147 Condition cond) { | |
| 1148 addrmod5(cond | B27 | B26 | l | L | coproc*B8, crd, src); | |
| 1149 } | |
| 1150 | |
| 1151 | |
| 1152 void Assembler::ldc(Coprocessor coproc, | |
| 1153 CRegister crd, | |
| 1154 Register rn, | |
| 1155 int option, | |
| 1156 LFlag l, | |
| 1157 Condition cond) { | |
| 1158 // unindexed addressing | |
| 1159 ASSERT(is_uint8(option)); | |
| 1160 emit(cond | B27 | B26 | U | l | L | rn.code()*B16 | crd.code()*B12 | | |
| 1161 coproc*B8 | (option & 255)); | |
| 1162 } | |
| 1163 | |
| 1164 | |
| 1165 void Assembler::ldc2(Coprocessor coproc, | |
| 1166 CRegister crd, | |
| 1167 const MemOperand& src, | |
| 1168 LFlag l) { // v5 and above | |
| 1169 ldc(coproc, crd, src, l, static_cast<Condition>(nv)); | |
| 1170 } | |
| 1171 | |
| 1172 | |
| 1173 void Assembler::ldc2(Coprocessor coproc, | |
| 1174 CRegister crd, | |
| 1175 Register rn, | |
| 1176 int option, | |
| 1177 LFlag l) { // v5 and above | |
| 1178 ldc(coproc, crd, rn, option, l, static_cast<Condition>(nv)); | |
| 1179 } | |
| 1180 | |
| 1181 | |
| 1182 void Assembler::stc(Coprocessor coproc, | |
| 1183 CRegister crd, | |
| 1184 const MemOperand& dst, | |
| 1185 LFlag l, | |
| 1186 Condition cond) { | |
| 1187 addrmod5(cond | B27 | B26 | l | coproc*B8, crd, dst); | |
| 1188 } | |
| 1189 | |
| 1190 | |
| 1191 void Assembler::stc(Coprocessor coproc, | |
| 1192 CRegister crd, | |
| 1193 Register rn, | |
| 1194 int option, | |
| 1195 LFlag l, | |
| 1196 Condition cond) { | |
| 1197 // unindexed addressing | |
| 1198 ASSERT(is_uint8(option)); | |
| 1199 emit(cond | B27 | B26 | U | l | rn.code()*B16 | crd.code()*B12 | | |
| 1200 coproc*B8 | (option & 255)); | |
| 1201 } | |
| 1202 | |
| 1203 | |
| 1204 void Assembler::stc2(Coprocessor | |
| 1205 coproc, CRegister crd, | |
| 1206 const MemOperand& dst, | |
| 1207 LFlag l) { // v5 and above | |
| 1208 stc(coproc, crd, dst, l, static_cast<Condition>(nv)); | |
| 1209 } | |
| 1210 | |
| 1211 | |
| 1212 void Assembler::stc2(Coprocessor coproc, | |
| 1213 CRegister crd, | |
| 1214 Register rn, | |
| 1215 int option, | |
| 1216 LFlag l) { // v5 and above | |
| 1217 stc(coproc, crd, rn, option, l, static_cast<Condition>(nv)); | |
| 1218 } | |
| 1219 | |
| 1220 | |
| 1221 // Pseudo instructions | |
| 1222 void Assembler::lea(Register dst, | |
| 1223 const MemOperand& x, | |
| 1224 SBit s, | |
| 1225 Condition cond) { | |
| 1226 int am = x.am_; | |
| 1227 if (!x.rm_.is_valid()) { | |
| 1228 // immediate offset | |
| 1229 if ((am & P) == 0) // post indexing | |
| 1230 mov(dst, Operand(x.rn_), s, cond); | |
| 1231 else if ((am & U) == 0) // negative indexing | |
| 1232 sub(dst, x.rn_, Operand(x.offset_), s, cond); | |
| 1233 else | |
| 1234 add(dst, x.rn_, Operand(x.offset_), s, cond); | |
| 1235 } else { | |
| 1236 // Register offset (shift_imm_ and shift_op_ are 0) or scaled | |
| 1237 // register offset the constructors make sure than both shift_imm_ | |
| 1238 // and shift_op_ are initialized. | |
| 1239 ASSERT(!x.rm_.is(pc)); | |
| 1240 if ((am & P) == 0) // post indexing | |
| 1241 mov(dst, Operand(x.rn_), s, cond); | |
| 1242 else if ((am & U) == 0) // negative indexing | |
| 1243 sub(dst, x.rn_, Operand(x.rm_, x.shift_op_, x.shift_imm_), s, cond); | |
| 1244 else | |
| 1245 add(dst, x.rn_, Operand(x.rm_, x.shift_op_, x.shift_imm_), s, cond); | |
| 1246 } | |
| 1247 } | |
| 1248 | |
| 1249 | |
| 1250 // Debugging | |
| 1251 void Assembler::RecordComment(const char* msg) { | |
| 1252 if (FLAG_debug_code) { | |
| 1253 CheckBuffer(); | |
| 1254 RecordRelocInfo(RelocInfo::COMMENT, reinterpret_cast<intptr_t>(msg)); | |
| 1255 } | |
| 1256 } | |
| 1257 | |
| 1258 | |
| 1259 void Assembler::RecordPosition(int pos) { | |
| 1260 if (pos == RelocInfo::kNoPosition) return; | |
| 1261 ASSERT(pos >= 0); | |
| 1262 current_position_ = pos; | |
| 1263 WriteRecordedPositions(); | |
| 1264 } | |
| 1265 | |
| 1266 | |
| 1267 void Assembler::RecordStatementPosition(int pos) { | |
| 1268 if (pos == RelocInfo::kNoPosition) return; | |
| 1269 ASSERT(pos >= 0); | |
| 1270 current_statement_position_ = pos; | |
| 1271 WriteRecordedPositions(); | |
| 1272 } | |
| 1273 | |
| 1274 | |
| 1275 void Assembler::WriteRecordedPositions() { | |
| 1276 // Write the statement position if it is different from what was written last | |
| 1277 // time. | |
| 1278 if (current_statement_position_ != written_statement_position_) { | |
| 1279 CheckBuffer(); | |
| 1280 RecordRelocInfo(RelocInfo::STATEMENT_POSITION, current_statement_position_); | |
| 1281 written_statement_position_ = current_statement_position_; | |
| 1282 } | |
| 1283 | |
| 1284 // Write the position if it is different from what was written last time and | |
| 1285 // also different from the written statement position. | |
| 1286 if (current_position_ != written_position_ && | |
| 1287 current_position_ != written_statement_position_) { | |
| 1288 CheckBuffer(); | |
| 1289 RecordRelocInfo(RelocInfo::POSITION, current_position_); | |
| 1290 written_position_ = current_position_; | |
| 1291 } | |
| 1292 } | |
| 1293 | |
| 1294 | |
| 1295 void Assembler::GrowBuffer() { | |
| 1296 if (!own_buffer_) FATAL("external code buffer is too small"); | |
| 1297 | |
| 1298 // compute new buffer size | |
| 1299 CodeDesc desc; // the new buffer | |
| 1300 if (buffer_size_ < 4*KB) { | |
| 1301 desc.buffer_size = 4*KB; | |
| 1302 } else if (buffer_size_ < 1*MB) { | |
| 1303 desc.buffer_size = 2*buffer_size_; | |
| 1304 } else { | |
| 1305 desc.buffer_size = buffer_size_ + 1*MB; | |
| 1306 } | |
| 1307 CHECK_GT(desc.buffer_size, 0); // no overflow | |
| 1308 | |
| 1309 // setup new buffer | |
| 1310 desc.buffer = NewArray<byte>(desc.buffer_size); | |
| 1311 | |
| 1312 desc.instr_size = pc_offset(); | |
| 1313 desc.reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos(); | |
| 1314 | |
| 1315 // copy the data | |
| 1316 int pc_delta = desc.buffer - buffer_; | |
| 1317 int rc_delta = (desc.buffer + desc.buffer_size) - (buffer_ + buffer_size_); | |
| 1318 memmove(desc.buffer, buffer_, desc.instr_size); | |
| 1319 memmove(reloc_info_writer.pos() + rc_delta, | |
| 1320 reloc_info_writer.pos(), desc.reloc_size); | |
| 1321 | |
| 1322 // switch buffers | |
| 1323 DeleteArray(buffer_); | |
| 1324 buffer_ = desc.buffer; | |
| 1325 buffer_size_ = desc.buffer_size; | |
| 1326 pc_ += pc_delta; | |
| 1327 reloc_info_writer.Reposition(reloc_info_writer.pos() + rc_delta, | |
| 1328 reloc_info_writer.last_pc() + pc_delta); | |
| 1329 | |
| 1330 // none of our relocation types are pc relative pointing outside the code | |
| 1331 // buffer nor pc absolute pointing inside the code buffer, so there is no need | |
| 1332 // to relocate any emitted relocation entries | |
| 1333 | |
| 1334 // relocate pending relocation entries | |
| 1335 for (int i = 0; i < num_prinfo_; i++) { | |
| 1336 RelocInfo& rinfo = prinfo_[i]; | |
| 1337 ASSERT(rinfo.rmode() != RelocInfo::COMMENT && | |
| 1338 rinfo.rmode() != RelocInfo::POSITION); | |
| 1339 rinfo.set_pc(rinfo.pc() + pc_delta); | |
| 1340 } | |
| 1341 } | |
| 1342 | |
| 1343 | |
| 1344 void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) { | |
| 1345 RelocInfo rinfo(pc_, rmode, data); // we do not try to reuse pool constants | |
| 1346 if (rmode >= RelocInfo::COMMENT && rmode <= RelocInfo::STATEMENT_POSITION) { | |
| 1347 // adjust code for new modes | |
| 1348 ASSERT(RelocInfo::IsComment(rmode) || RelocInfo::IsPosition(rmode)); | |
| 1349 // these modes do not need an entry in the constant pool | |
| 1350 } else { | |
| 1351 ASSERT(num_prinfo_ < kMaxNumPRInfo); | |
| 1352 prinfo_[num_prinfo_++] = rinfo; | |
| 1353 // Make sure the constant pool is not emitted in place of the next | |
| 1354 // instruction for which we just recorded relocation info | |
| 1355 BlockConstPoolBefore(pc_offset() + kInstrSize); | |
| 1356 } | |
| 1357 if (rinfo.rmode() != RelocInfo::NONE) { | |
| 1358 // Don't record external references unless the heap will be serialized. | |
| 1359 if (rmode == RelocInfo::EXTERNAL_REFERENCE && | |
| 1360 !Serializer::enabled() && | |
| 1361 !FLAG_debug_code) { | |
| 1362 return; | |
| 1363 } | |
| 1364 ASSERT(buffer_space() >= kMaxRelocSize); // too late to grow buffer here | |
| 1365 reloc_info_writer.Write(&rinfo); | |
| 1366 } | |
| 1367 } | |
| 1368 | |
| 1369 | |
| 1370 void Assembler::CheckConstPool(bool force_emit, bool require_jump) { | |
| 1371 // Calculate the offset of the next check. It will be overwritten | |
| 1372 // when a const pool is generated or when const pools are being | |
| 1373 // blocked for a specific range. | |
| 1374 next_buffer_check_ = pc_offset() + kCheckConstInterval; | |
| 1375 | |
| 1376 // There is nothing to do if there are no pending relocation info entries | |
| 1377 if (num_prinfo_ == 0) return; | |
| 1378 | |
| 1379 // We emit a constant pool at regular intervals of about kDistBetweenPools | |
| 1380 // or when requested by parameter force_emit (e.g. after each function). | |
| 1381 // We prefer not to emit a jump unless the max distance is reached or if we | |
| 1382 // are running low on slots, which can happen if a lot of constants are being | |
| 1383 // emitted (e.g. --debug-code and many static references). | |
| 1384 int dist = pc_offset() - last_const_pool_end_; | |
| 1385 if (!force_emit && dist < kMaxDistBetweenPools && | |
| 1386 (require_jump || dist < kDistBetweenPools) && | |
| 1387 // TODO(1236125): Cleanup the "magic" number below. We know that | |
| 1388 // the code generation will test every kCheckConstIntervalInst. | |
| 1389 // Thus we are safe as long as we generate less than 7 constant | |
| 1390 // entries per instruction. | |
| 1391 (num_prinfo_ < (kMaxNumPRInfo - (7 * kCheckConstIntervalInst)))) { | |
| 1392 return; | |
| 1393 } | |
| 1394 | |
| 1395 // If we did not return by now, we need to emit the constant pool soon. | |
| 1396 | |
| 1397 // However, some small sequences of instructions must not be broken up by the | |
| 1398 // insertion of a constant pool; such sequences are protected by setting | |
| 1399 // no_const_pool_before_, which is checked here. Also, recursive calls to | |
| 1400 // CheckConstPool are blocked by no_const_pool_before_. | |
| 1401 if (pc_offset() < no_const_pool_before_) { | |
| 1402 // Emission is currently blocked; make sure we try again as soon as possible | |
| 1403 next_buffer_check_ = no_const_pool_before_; | |
| 1404 | |
| 1405 // Something is wrong if emission is forced and blocked at the same time | |
| 1406 ASSERT(!force_emit); | |
| 1407 return; | |
| 1408 } | |
| 1409 | |
| 1410 int jump_instr = require_jump ? kInstrSize : 0; | |
| 1411 | |
| 1412 // Check that the code buffer is large enough before emitting the constant | |
| 1413 // pool and relocation information (include the jump over the pool and the | |
| 1414 // constant pool marker). | |
| 1415 int max_needed_space = | |
| 1416 jump_instr + kInstrSize + num_prinfo_*(kInstrSize + kMaxRelocSize); | |
| 1417 while (buffer_space() <= (max_needed_space + kGap)) GrowBuffer(); | |
| 1418 | |
| 1419 // Block recursive calls to CheckConstPool | |
| 1420 BlockConstPoolBefore(pc_offset() + jump_instr + kInstrSize + | |
| 1421 num_prinfo_*kInstrSize); | |
| 1422 // Don't bother to check for the emit calls below. | |
| 1423 next_buffer_check_ = no_const_pool_before_; | |
| 1424 | |
| 1425 // Emit jump over constant pool if necessary | |
| 1426 Label after_pool; | |
| 1427 if (require_jump) b(&after_pool); | |
| 1428 | |
| 1429 RecordComment("[ Constant Pool"); | |
| 1430 | |
| 1431 // Put down constant pool marker | |
| 1432 // "Undefined instruction" as specified by A3.1 Instruction set encoding | |
| 1433 emit(0x03000000 | num_prinfo_); | |
| 1434 | |
| 1435 // Emit constant pool entries | |
| 1436 for (int i = 0; i < num_prinfo_; i++) { | |
| 1437 RelocInfo& rinfo = prinfo_[i]; | |
| 1438 ASSERT(rinfo.rmode() != RelocInfo::COMMENT && | |
| 1439 rinfo.rmode() != RelocInfo::POSITION && | |
| 1440 rinfo.rmode() != RelocInfo::STATEMENT_POSITION); | |
| 1441 Instr instr = instr_at(rinfo.pc()); | |
| 1442 // Instruction to patch must be a ldr/str [pc, #offset] | |
| 1443 // P and U set, B and W clear, Rn == pc, offset12 still 0 | |
| 1444 ASSERT((instr & (7*B25 | P | U | B | W | 15*B16 | Off12Mask)) == | |
| 1445 (2*B25 | P | U | pc.code()*B16)); | |
| 1446 int delta = pc_ - rinfo.pc() - 8; | |
| 1447 ASSERT(delta >= -4); // instr could be ldr pc, [pc, #-4] followed by targ32 | |
| 1448 if (delta < 0) { | |
| 1449 instr &= ~U; | |
| 1450 delta = -delta; | |
| 1451 } | |
| 1452 ASSERT(is_uint12(delta)); | |
| 1453 instr_at_put(rinfo.pc(), instr + delta); | |
| 1454 emit(rinfo.data()); | |
| 1455 } | |
| 1456 num_prinfo_ = 0; | |
| 1457 last_const_pool_end_ = pc_offset(); | |
| 1458 | |
| 1459 RecordComment("]"); | |
| 1460 | |
| 1461 if (after_pool.is_linked()) { | |
| 1462 bind(&after_pool); | |
| 1463 } | |
| 1464 | |
| 1465 // Since a constant pool was just emitted, move the check offset forward by | |
| 1466 // the standard interval. | |
| 1467 next_buffer_check_ = pc_offset() + kCheckConstInterval; | |
| 1468 } | |
| 1469 | |
| 1470 | |
| 1471 } } // namespace v8::internal | |
| OLD | NEW |
|---|
Chromium Code Reviews
Issue 92068:
Move backend specific files to separate directories. (Closed)
