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| 1 // Copyright 2008 the V8 project authors. All rights reserved. |
| 2 // Redistribution and use in source and binary forms, with or without |
| 3 // modification, are permitted provided that the following conditions are |
| 4 // met: |
| 5 // |
| 6 // * Redistributions of source code must retain the above copyright |
| 7 // notice, this list of conditions and the following disclaimer. |
| 8 // * Redistributions in binary form must reproduce the above |
| 9 // copyright notice, this list of conditions and the following |
| 10 // disclaimer in the documentation and/or other materials provided |
| 11 // with the distribution. |
| 12 // * Neither the name of Google Inc. nor the names of its |
| 13 // contributors may be used to endorse or promote products derived |
| 14 // from this software without specific prior written permission. |
| 15 // |
| 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 17 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 18 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 19 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 20 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 21 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 22 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 23 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 24 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 25 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 26 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 |
| 28 #ifndef V8_CONSTANTS_ARM_H_ |
| 29 #define V8_CONSTANTS_ARM_H_ |
| 30 |
| 31 namespace assembler { namespace arm { |
| 32 |
| 33 // Defines constants and accessor classes to assemble, disassemble and |
| 34 // simulate ARM instructions. |
| 35 // |
| 36 // Section references in the code refer to the "ARM Architecture Reference |
| 37 // Manual" from July 2005 (available at http://www.arm.com/miscPDFs/14128.pdf) |
| 38 // |
| 39 // Constants for specific fields are defined in their respective named enums. |
| 40 // General constants are in an anonymous enum in class Instr. |
| 41 |
| 42 typedef unsigned char byte; |
| 43 |
| 44 // Values for the condition field as defined in section A3.2 |
| 45 enum Condition { |
| 46 no_condition = -1, |
| 47 EQ = 0, // equal |
| 48 NE = 1, // not equal |
| 49 CS = 2, // carry set/unsigned higher or same |
| 50 CC = 3, // carry clear/unsigned lower |
| 51 MI = 4, // minus/negative |
| 52 PL = 5, // plus/positive or zero |
| 53 VS = 6, // overflow |
| 54 VC = 7, // no overflow |
| 55 HI = 8, // unsigned higher |
| 56 LS = 9, // unsigned lower or same |
| 57 GE = 10, // signed greater than or equal |
| 58 LT = 11, // signed less than |
| 59 GT = 12, // signed greater than |
| 60 LE = 13, // signed less than or equal |
| 61 AL = 14, // always (unconditional) |
| 62 special_condition = 15, // special condition (refer to section A3.2.1) |
| 63 max_condition = 16 |
| 64 }; |
| 65 |
| 66 |
| 67 // Opcodes for Data-processing instructions (instructions with a type 0 and 1) |
| 68 // as defined in section A3.4 |
| 69 enum Opcode { |
| 70 no_operand = -1, |
| 71 AND = 0, // Logical AND |
| 72 EOR = 1, // Logical Exclusive OR |
| 73 SUB = 2, // Subtract |
| 74 RSB = 3, // Reverse Subtract |
| 75 ADD = 4, // Add |
| 76 ADC = 5, // Add with Carry |
| 77 SBC = 6, // Subtract with Carry |
| 78 RSC = 7, // Reverse Subtract with Carry |
| 79 TST = 8, // Test |
| 80 TEQ = 9, // Test Equivalence |
| 81 CMP = 10, // Compare |
| 82 CMN = 11, // Compare Negated |
| 83 ORR = 12, // Logical (inclusive) OR |
| 84 MOV = 13, // Move |
| 85 BIC = 14, // Bit Clear |
| 86 MVN = 15, // Move Not |
| 87 max_operand = 16 |
| 88 }; |
| 89 |
| 90 |
| 91 // Shifter types for Data-processing operands as defined in section A5.1.2. |
| 92 enum Shift { |
| 93 no_shift = -1, |
| 94 LSL = 0, // Logical shift left |
| 95 LSR = 1, // Logical shift right |
| 96 ASR = 2, // Arithmetic shift right |
| 97 ROR = 3, // Rotate right |
| 98 max_shift = 4 |
| 99 }; |
| 100 |
| 101 |
| 102 // Special Software Interrupt codes when used in the presence of the ARM |
| 103 // simulator. |
| 104 enum SoftwareInterruptCodes { |
| 105 // transition to C code |
| 106 call_rt_r5 = 0x10, |
| 107 call_rt_r2 = 0x11, |
| 108 // break point |
| 109 break_point = 0x20, |
| 110 // FP operations. These simulate calling into C for a moment to do fp ops. |
| 111 // They should trash all caller-save registers. |
| 112 simulator_fp_add = 0x21, |
| 113 simulator_fp_sub = 0x22, |
| 114 simulator_fp_mul = 0x23 |
| 115 }; |
| 116 |
| 117 |
| 118 typedef int32_t instr_t; |
| 119 |
| 120 |
| 121 // The class Instr enables access to individual fields defined in the ARM |
| 122 // architecture instruction set encoding as described in figure A3-1. |
| 123 // |
| 124 // Example: Test whether the instruction at ptr does set the condition code |
| 125 // bits. |
| 126 // |
| 127 // bool InstructionSetsConditionCodes(byte* ptr) { |
| 128 // Instr* instr = Instr::At(ptr); |
| 129 // int type = instr->TypeField(); |
| 130 // return ((type == 0) || (type == 1)) && instr->HasS(); |
| 131 // } |
| 132 // |
| 133 class Instr { |
| 134 public: |
| 135 enum { |
| 136 kInstrSize = 4, |
| 137 kInstrSizeLog2 = 2, |
| 138 kPCReadOffset = 8 |
| 139 }; |
| 140 |
| 141 // Get the raw instruction bits. |
| 142 inline instr_t InstructionBits() const { |
| 143 return *reinterpret_cast<const instr_t*>(this); |
| 144 } |
| 145 |
| 146 // Set the raw instruction bits to value. |
| 147 inline void SetInstructionBits(instr_t value) { |
| 148 *reinterpret_cast<instr_t*>(this) = value; |
| 149 } |
| 150 |
| 151 // Read one particular bit out of the instruction bits. |
| 152 inline int Bit(int nr) const { |
| 153 return (InstructionBits() >> nr) & 1; |
| 154 } |
| 155 |
| 156 // Read a bit field out of the instruction bits. |
| 157 inline int Bits(int hi, int lo) const { |
| 158 return (InstructionBits() >> lo) & ((2 << (hi - lo)) - 1); |
| 159 } |
| 160 |
| 161 |
| 162 // Accessors for the different named fields used in the ARM encoding. |
| 163 // The naming of these accessor corresponds to figure A3-1. |
| 164 // Generally applicable fields |
| 165 inline Condition ConditionField() const { |
| 166 return static_cast<Condition>(Bits(31, 28)); |
| 167 } |
| 168 inline int TypeField() const { return Bits(27, 25); } |
| 169 |
| 170 inline int RnField() const { return Bits(19, 16); } |
| 171 inline int RdField() const { return Bits(15, 12); } |
| 172 |
| 173 // Fields used in Data processing instructions |
| 174 inline Opcode OpcodeField() const { |
| 175 return static_cast<Opcode>(Bits(24, 21)); |
| 176 } |
| 177 inline int SField() const { return Bit(20); } |
| 178 // with register |
| 179 inline int RmField() const { return Bits(3, 0); } |
| 180 inline Shift ShiftField() const { return static_cast<Shift>(Bits(6, 5)); } |
| 181 inline int RegShiftField() const { return Bit(4); } |
| 182 inline int RsField() const { return Bits(11, 8); } |
| 183 inline int ShiftAmountField() const { return Bits(11, 7); } |
| 184 // with immediate |
| 185 inline int RotateField() const { return Bits(11, 8); } |
| 186 inline int Immed8Field() const { return Bits(7, 0); } |
| 187 |
| 188 // Fields used in Load/Store instructions |
| 189 inline int PUField() const { return Bits(24, 23); } |
| 190 inline int BField() const { return Bit(22); } |
| 191 inline int WField() const { return Bit(21); } |
| 192 inline int LField() const { return Bit(20); } |
| 193 // with register uses same fields as Data processing instructions above |
| 194 // with immediate |
| 195 inline int Offset12Field() const { return Bits(11, 0); } |
| 196 // multiple |
| 197 inline int RlistField() const { return Bits(15, 0); } |
| 198 // extra loads and stores |
| 199 inline int SignField() const { return Bit(6); } |
| 200 inline int HField() const { return Bit(5); } |
| 201 inline int ImmedHField() const { return Bits(11, 8); } |
| 202 inline int ImmedLField() const { return Bits(3, 0); } |
| 203 |
| 204 // Fields used in Branch instructions |
| 205 inline int LinkField() const { return Bit(24); } |
| 206 inline int SImmed24Field() const { return ((InstructionBits() << 8) >> 8); } |
| 207 |
| 208 // Fields used in Software interrupt instructions |
| 209 inline SoftwareInterruptCodes SwiField() const { |
| 210 return static_cast<SoftwareInterruptCodes>(Bits(23, 0)); |
| 211 } |
| 212 |
| 213 // Test for special encodings of type 0 instructions (extra loads and stores, |
| 214 // as well as multiplications). |
| 215 inline bool IsSpecialType0() const { return (Bit(7) == 1) && (Bit(4) == 1); } |
| 216 |
| 217 // Special accessors that test for existence of a value. |
| 218 inline bool HasS() const { return SField() == 1; } |
| 219 inline bool HasB() const { return BField() == 1; } |
| 220 inline bool HasW() const { return WField() == 1; } |
| 221 inline bool HasL() const { return LField() == 1; } |
| 222 inline bool HasSign() const { return SignField() == 1; } |
| 223 inline bool HasH() const { return HField() == 1; } |
| 224 inline bool HasLink() const { return LinkField() == 1; } |
| 225 |
| 226 // Instructions are read of out a code stream. The only way to get a |
| 227 // reference to an instruction is to convert a pointer. There is no way |
| 228 // to allocate or create instances of class Instr. |
| 229 // Use the At(pc) function to create references to Instr. |
| 230 static Instr* At(byte* pc) { return reinterpret_cast<Instr*>(pc); } |
| 231 |
| 232 private: |
| 233 // We need to prevent the creation of instances of class Instr. |
| 234 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr); |
| 235 }; |
| 236 |
| 237 |
| 238 } } // namespace assembler::arm |
| 239 |
| 240 #endif // V8_CONSTANTS_ARM_H_ |
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