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| 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
| 2 // All Rights Reserved. |
| 3 // |
| 4 // Redistribution and use in source and binary forms, with or without |
| 5 // modification, are permitted provided that the following conditions |
| 6 // are met: |
| 7 // |
| 8 // - Redistributions of source code must retain the above copyright notice, |
| 9 // this list of conditions and the following disclaimer. |
| 10 // |
| 11 // - Redistribution in binary form must reproduce the above copyright |
| 12 // notice, this list of conditions and the following disclaimer in the |
| 13 // documentation and/or other materials provided with the |
| 14 // distribution. |
| 15 // |
| 16 // - Neither the name of Sun Microsystems or the names of contributors may |
| 17 // be used to endorse or promote products derived from this software without |
| 18 // specific prior written permission. |
| 19 // |
| 20 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 21 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 22 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 23 // FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 24 // COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 25 // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 26 // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| 27 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 28 // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
| 29 // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 30 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED |
| 31 // OF THE POSSIBILITY OF SUCH DAMAGE. |
| 32 |
| 33 // The original source code covered by the above license above has been modified |
| 34 // significantly by Google Inc. |
| 35 // Copyright 2006-2008 the V8 project authors. All rights reserved. |
| 36 |
| 37 #ifndef V8_ASSEMBLER_ARM_INL_H_ |
| 38 #define V8_ASSEMBLER_ARM_INL_H_ |
| 39 |
| 40 #include "arm/assembler-arm.h" |
| 41 #include "cpu.h" |
| 42 |
| 43 |
| 44 namespace v8 { namespace internal { |
| 45 |
| 46 Condition NegateCondition(Condition cc) { |
| 47 ASSERT(cc != al); |
| 48 return static_cast<Condition>(cc ^ ne); |
| 49 } |
| 50 |
| 51 |
| 52 void RelocInfo::apply(int delta) { |
| 53 if (RelocInfo::IsInternalReference(rmode_)) { |
| 54 // absolute code pointer inside code object moves with the code object. |
| 55 int32_t* p = reinterpret_cast<int32_t*>(pc_); |
| 56 *p += delta; // relocate entry |
| 57 } |
| 58 // We do not use pc relative addressing on ARM, so there is |
| 59 // nothing else to do. |
| 60 } |
| 61 |
| 62 |
| 63 Address RelocInfo::target_address() { |
| 64 ASSERT(IsCodeTarget(rmode_) || rmode_ == RUNTIME_ENTRY); |
| 65 return Assembler::target_address_at(pc_); |
| 66 } |
| 67 |
| 68 |
| 69 Address RelocInfo::target_address_address() { |
| 70 ASSERT(IsCodeTarget(rmode_) || rmode_ == RUNTIME_ENTRY); |
| 71 return reinterpret_cast<Address>(Assembler::target_address_address_at(pc_)); |
| 72 } |
| 73 |
| 74 |
| 75 void RelocInfo::set_target_address(Address target) { |
| 76 ASSERT(IsCodeTarget(rmode_) || rmode_ == RUNTIME_ENTRY); |
| 77 Assembler::set_target_address_at(pc_, target); |
| 78 } |
| 79 |
| 80 |
| 81 Object* RelocInfo::target_object() { |
| 82 ASSERT(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT); |
| 83 return reinterpret_cast<Object*>(Assembler::target_address_at(pc_)); |
| 84 } |
| 85 |
| 86 |
| 87 Object** RelocInfo::target_object_address() { |
| 88 ASSERT(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT); |
| 89 return reinterpret_cast<Object**>(Assembler::target_address_address_at(pc_)); |
| 90 } |
| 91 |
| 92 |
| 93 void RelocInfo::set_target_object(Object* target) { |
| 94 ASSERT(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT); |
| 95 Assembler::set_target_address_at(pc_, reinterpret_cast<Address>(target)); |
| 96 } |
| 97 |
| 98 |
| 99 Address* RelocInfo::target_reference_address() { |
| 100 ASSERT(rmode_ == EXTERNAL_REFERENCE); |
| 101 return reinterpret_cast<Address*>(Assembler::target_address_address_at(pc_)); |
| 102 } |
| 103 |
| 104 |
| 105 Address RelocInfo::call_address() { |
| 106 ASSERT(IsCallInstruction()); |
| 107 UNIMPLEMENTED(); |
| 108 return NULL; |
| 109 } |
| 110 |
| 111 |
| 112 void RelocInfo::set_call_address(Address target) { |
| 113 ASSERT(IsCallInstruction()); |
| 114 UNIMPLEMENTED(); |
| 115 } |
| 116 |
| 117 |
| 118 Object* RelocInfo::call_object() { |
| 119 ASSERT(IsCallInstruction()); |
| 120 UNIMPLEMENTED(); |
| 121 return NULL; |
| 122 } |
| 123 |
| 124 |
| 125 Object** RelocInfo::call_object_address() { |
| 126 ASSERT(IsCallInstruction()); |
| 127 UNIMPLEMENTED(); |
| 128 return NULL; |
| 129 } |
| 130 |
| 131 |
| 132 void RelocInfo::set_call_object(Object* target) { |
| 133 ASSERT(IsCallInstruction()); |
| 134 UNIMPLEMENTED(); |
| 135 } |
| 136 |
| 137 |
| 138 bool RelocInfo::IsCallInstruction() { |
| 139 UNIMPLEMENTED(); |
| 140 return false; |
| 141 } |
| 142 |
| 143 |
| 144 Operand::Operand(int32_t immediate, RelocInfo::Mode rmode) { |
| 145 rm_ = no_reg; |
| 146 imm32_ = immediate; |
| 147 rmode_ = rmode; |
| 148 } |
| 149 |
| 150 |
| 151 Operand::Operand(const char* s) { |
| 152 rm_ = no_reg; |
| 153 imm32_ = reinterpret_cast<int32_t>(s); |
| 154 rmode_ = RelocInfo::EMBEDDED_STRING; |
| 155 } |
| 156 |
| 157 |
| 158 Operand::Operand(const ExternalReference& f) { |
| 159 rm_ = no_reg; |
| 160 imm32_ = reinterpret_cast<int32_t>(f.address()); |
| 161 rmode_ = RelocInfo::EXTERNAL_REFERENCE; |
| 162 } |
| 163 |
| 164 |
| 165 Operand::Operand(Object** opp) { |
| 166 rm_ = no_reg; |
| 167 imm32_ = reinterpret_cast<int32_t>(opp); |
| 168 rmode_ = RelocInfo::NONE; |
| 169 } |
| 170 |
| 171 |
| 172 Operand::Operand(Context** cpp) { |
| 173 rm_ = no_reg; |
| 174 imm32_ = reinterpret_cast<int32_t>(cpp); |
| 175 rmode_ = RelocInfo::NONE; |
| 176 } |
| 177 |
| 178 |
| 179 Operand::Operand(Smi* value) { |
| 180 rm_ = no_reg; |
| 181 imm32_ = reinterpret_cast<intptr_t>(value); |
| 182 rmode_ = RelocInfo::NONE; |
| 183 } |
| 184 |
| 185 |
| 186 Operand::Operand(Register rm) { |
| 187 rm_ = rm; |
| 188 rs_ = no_reg; |
| 189 shift_op_ = LSL; |
| 190 shift_imm_ = 0; |
| 191 } |
| 192 |
| 193 |
| 194 bool Operand::is_reg() const { |
| 195 return rm_.is_valid() && |
| 196 rs_.is(no_reg) && |
| 197 shift_op_ == LSL && |
| 198 shift_imm_ == 0; |
| 199 } |
| 200 |
| 201 |
| 202 void Assembler::CheckBuffer() { |
| 203 if (buffer_space() <= kGap) { |
| 204 GrowBuffer(); |
| 205 } |
| 206 if (pc_offset() > next_buffer_check_) { |
| 207 CheckConstPool(false, true); |
| 208 } |
| 209 } |
| 210 |
| 211 |
| 212 void Assembler::emit(Instr x) { |
| 213 CheckBuffer(); |
| 214 *reinterpret_cast<Instr*>(pc_) = x; |
| 215 pc_ += kInstrSize; |
| 216 } |
| 217 |
| 218 |
| 219 Address Assembler::target_address_address_at(Address pc) { |
| 220 Instr instr = Memory::int32_at(pc); |
| 221 // Verify that the instruction at pc is a ldr<cond> <Rd>, [pc +/- offset_12]. |
| 222 ASSERT((instr & 0x0f7f0000) == 0x051f0000); |
| 223 int offset = instr & 0xfff; // offset_12 is unsigned |
| 224 if ((instr & (1 << 23)) == 0) offset = -offset; // U bit defines offset sign |
| 225 // Verify that the constant pool comes after the instruction referencing it. |
| 226 ASSERT(offset >= -4); |
| 227 return pc + offset + 8; |
| 228 } |
| 229 |
| 230 |
| 231 Address Assembler::target_address_at(Address pc) { |
| 232 return Memory::Address_at(target_address_address_at(pc)); |
| 233 } |
| 234 |
| 235 |
| 236 void Assembler::set_target_address_at(Address pc, Address target) { |
| 237 Memory::Address_at(target_address_address_at(pc)) = target; |
| 238 // Intuitively, we would think it is necessary to flush the instruction cache |
| 239 // after patching a target address in the code as follows: |
| 240 // CPU::FlushICache(pc, sizeof(target)); |
| 241 // However, on ARM, no instruction was actually patched by the assignment |
| 242 // above; the target address is not part of an instruction, it is patched in |
| 243 // the constant pool and is read via a data access; the instruction accessing |
| 244 // this address in the constant pool remains unchanged. |
| 245 } |
| 246 |
| 247 } } // namespace v8::internal |
| 248 |
| 249 #endif // V8_ASSEMBLER_ARM_INL_H_ |
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