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1 // Copyright 2008 the V8 project authors. All rights reserved. | 1 // Copyright 2008 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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26 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | 26 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | 27 |
28 #ifndef V8_CONSTANTS_ARM_H_ | 28 #ifndef V8_CONSTANTS_ARM_H_ |
29 #define V8_CONSTANTS_ARM_H_ | 29 #define V8_CONSTANTS_ARM_H_ |
30 | 30 |
31 namespace assembler { namespace arm { | 31 namespace assembler { namespace arm { |
32 | 32 |
33 // Defines constants and accessor classes to assemble, disassemble and | 33 // Defines constants and accessor classes to assemble, disassemble and |
34 // simulate ARM instructions. | 34 // simulate ARM instructions. |
35 // | 35 // |
| 36 // Section references in the code refer to the "ARM Architecture Reference |
| 37 // Manual" from July 2005 (available at http://www.arm.com/miscPDFs/14128.pdf) |
| 38 // |
36 // Constants for specific fields are defined in their respective named enums. | 39 // Constants for specific fields are defined in their respective named enums. |
37 // General constants are in an anonymous enum in class Instr. | 40 // General constants are in an anonymous enum in class Instr. |
38 | 41 |
39 typedef unsigned char byte; | 42 typedef unsigned char byte; |
40 | 43 |
| 44 // Values for the condition field as defined in section A3.2 |
41 enum Condition { | 45 enum Condition { |
42 no_condition = -1, | 46 no_condition = -1, |
43 EQ = 0, | 47 EQ = 0, // equal |
44 NE = 1, | 48 NE = 1, // not equal |
45 CS = 2, | 49 CS = 2, // carry set/unsigned higher or same |
46 CC = 3, | 50 CC = 3, // carry clear/unsigned lower |
47 MI = 4, | 51 MI = 4, // minus/negative |
48 PL = 5, | 52 PL = 5, // plus/positive or zero |
49 VS = 6, | 53 VS = 6, // overflow |
50 VC = 7, | 54 VC = 7, // no overflow |
51 HI = 8, | 55 HI = 8, // unsigned higher |
52 LS = 9, | 56 LS = 9, // unsigned lower or same |
53 GE = 10, | 57 GE = 10, // signed greater than or equal |
54 LT = 11, | 58 LT = 11, // signed less than |
55 GT = 12, | 59 GT = 12, // signed greater than |
56 LE = 13, | 60 LE = 13, // signed less than or equal |
57 AL = 14, | 61 AL = 14, // always (unconditional) |
58 special_condition = 15 | 62 special_condition = 15, // special condition (refer to section A3.2.1) |
| 63 max_condition = 16 |
59 }; | 64 }; |
60 | 65 |
61 | 66 |
| 67 // Opcodes for Data-processing instructions (instructions with a type 0 and 1) |
| 68 // as defined in section A3.4 |
62 enum Opcode { | 69 enum Opcode { |
63 no_operand = -1, | 70 no_operand = -1, |
64 AND = 0, | 71 AND = 0, // Logical AND |
65 EOR = 1, | 72 EOR = 1, // Logical Exclusive OR |
66 SUB = 2, | 73 SUB = 2, // Subtract |
67 RSB = 3, | 74 RSB = 3, // Reverse Subtract |
68 ADD = 4, | 75 ADD = 4, // Add |
69 ADC = 5, | 76 ADC = 5, // Add with Carry |
70 SBC = 6, | 77 SBC = 6, // Subtract with Carry |
71 RSC = 7, | 78 RSC = 7, // Reverse Subtract with Carry |
72 TST = 8, | 79 TST = 8, // Test |
73 TEQ = 9, | 80 TEQ = 9, // Test Equivalence |
74 CMP = 10, | 81 CMP = 10, // Compare |
75 CMN = 11, | 82 CMN = 11, // Compare Negated |
76 ORR = 12, | 83 ORR = 12, // Logical (inclusive) OR |
77 MOV = 13, | 84 MOV = 13, // Move |
78 BIC = 14, | 85 BIC = 14, // Bit Clear |
79 MVN = 15 | 86 MVN = 15, // Move Not |
| 87 max_operand = 16 |
80 }; | 88 }; |
81 | 89 |
82 | 90 |
| 91 // Shifter types for Data-processing operands as defined in section A5.1.2. |
83 enum Shift { | 92 enum Shift { |
84 no_shift = -1, | 93 no_shift = -1, |
85 LSL = 0, | 94 LSL = 0, // Logical shift left |
86 LSR = 1, | 95 LSR = 1, // Logical shift right |
87 ASR = 2, | 96 ASR = 2, // Arithmetic shift right |
88 ROR = 3 | 97 ROR = 3, // Rotate right |
| 98 max_shift = 4 |
89 }; | 99 }; |
90 | 100 |
91 | 101 |
| 102 // Special Software Interrupt codes when used in the presence of the ARM |
| 103 // simulator. |
92 enum SoftwareInterruptCodes { | 104 enum SoftwareInterruptCodes { |
93 // transition to C code | 105 // transition to C code |
94 call_rt_r5 = 0x10, | 106 call_rt_r5 = 0x10, |
95 call_rt_r2 = 0x11, | 107 call_rt_r2 = 0x11, |
96 // break point | 108 // break point |
97 break_point = 0x20 | 109 break_point = 0x20 |
98 }; | 110 }; |
99 | 111 |
100 | 112 |
101 typedef int32_t instr_t; | 113 typedef int32_t instr_t; |
102 | 114 |
103 | 115 |
104 // The class Instr enables access to individual fields defined in the ARM | 116 // The class Instr enables access to individual fields defined in the ARM |
105 // architecture. | 117 // architecture instruction set encoding as described in figure A3-1. |
| 118 // |
| 119 // Example: Test whether the instruction at ptr does set the condition code |
| 120 // bits. |
| 121 // |
| 122 // bool InstructionSetsConditionCodes(byte* ptr) { |
| 123 // Instr *instr = Instr::At(ptr); |
| 124 // int type = instr->TypeField(); |
| 125 // return ((type == 0) || (type == 1)) && instr->HasS(); |
| 126 // } |
| 127 // |
106 class Instr { | 128 class Instr { |
107 public: | 129 public: |
108 enum { | 130 enum { |
109 kInstrSize = 4, | 131 kInstrSize = 4, |
110 kPCReadOffset = 8 | 132 kPCReadOffset = 8 |
111 }; | 133 }; |
112 | 134 |
113 // Get the raw instruction bits | 135 // Get the raw instruction bits. |
114 inline instr_t InstructionBits() const { | 136 inline instr_t InstructionBits() const { |
115 return *reinterpret_cast<const instr_t*>(this); | 137 return *reinterpret_cast<const instr_t*>(this); |
116 } | 138 } |
117 | 139 |
| 140 // Set the raw instruction bits to value. |
118 inline void SetInstructionBits(instr_t value) { | 141 inline void SetInstructionBits(instr_t value) { |
119 *reinterpret_cast<instr_t*>(this) = value; | 142 *reinterpret_cast<instr_t*>(this) = value; |
120 } | 143 } |
121 | 144 |
| 145 // Read one particular bit out of the instruction bits. |
122 inline int Bit(int nr) const { | 146 inline int Bit(int nr) const { |
123 return (InstructionBits() >> nr) & 1; | 147 return (InstructionBits() >> nr) & 1; |
124 } | 148 } |
125 | 149 |
| 150 // Read a bit field out of the instruction bits. |
126 inline int Bits(int hi, int lo) const { | 151 inline int Bits(int hi, int lo) const { |
127 return (InstructionBits() >> lo) & ((2 << (hi - lo)) - 1); | 152 return (InstructionBits() >> lo) & ((2 << (hi - lo)) - 1); |
128 } | 153 } |
129 | 154 |
130 | 155 |
131 // Accessors for the different named fields used in the ARM encoding. | 156 // Accessors for the different named fields used in the ARM encoding. |
| 157 // The naming of these accessor corresponds to figure A3-1. |
132 // Generally applicable fields | 158 // Generally applicable fields |
133 inline Condition ConditionField() const { | 159 inline Condition ConditionField() const { |
134 return static_cast<Condition>(Bits(31, 28)); | 160 return static_cast<Condition>(Bits(31, 28)); |
135 } | 161 } |
136 inline int TypeField() const { return Bits(27, 25); } | 162 inline int TypeField() const { return Bits(27, 25); } |
137 | 163 |
138 inline int RnField() const { return Bits(19, 16); } | 164 inline int RnField() const { return Bits(19, 16); } |
139 inline int RdField() const { return Bits(15, 12); } | 165 inline int RdField() const { return Bits(15, 12); } |
140 | 166 |
141 // Fields used in Data processing instructions | 167 // Fields used in Data processing instructions |
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199 | 225 |
200 private: | 226 private: |
201 // We need to prevent the creation of instances of class Instr. | 227 // We need to prevent the creation of instances of class Instr. |
202 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr); | 228 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr); |
203 }; | 229 }; |
204 | 230 |
205 | 231 |
206 } } // namespace assembler::arm | 232 } } // namespace assembler::arm |
207 | 233 |
208 #endif // V8_CONSTANTS_ARM_H_ | 234 #endif // V8_CONSTANTS_ARM_H_ |
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