Fix issues with compiling V8 with LLVM Clang...

src/mips/simulator-mips.cc

 // Copyright 2010 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 13 matching lines @@
 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 #include <stdlib.h>
 #include <cstdarg>
 #include "v8.h"
 
 #include "disasm.h"
 #include "assembler.h"
-#include "globals.h"    // Need the bit_cast
+#include "globals.h"    // Need the BitCast
 #include "mips/constants-mips.h"
 #include "mips/simulator-mips.h"
 
 namespace v8i = v8::internal;
 
 #if !defined(__mips)
 
 // Only build the simulator if not compiling for real MIPS hardware.
 namespace assembler {
 namespace mips {
@@ skipping 552 matching lines @@
   registers_[reg] = (reg == 0) ? 0 : value;
 }
 
 void Simulator::set_fpu_register(int fpureg, int32_t value) {
   ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters));
   FPUregisters_[fpureg] = value;
 }
 
 void Simulator::set_fpu_register_double(int fpureg, double value) {
   ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters) && ((fpureg % 2) == 0));
-  *v8i::bit_cast<double*, int32_t*>(&FPUregisters_[fpureg]) = value;
+  *v8i::BitCast<double*, int32_t*>(&FPUregisters_[fpureg]) = value;
 }
 
 
 // Get the register from the architecture state. This function does handle
 // the special case of accessing the PC register.
 int32_t Simulator::get_register(int reg) const {
   ASSERT((reg >= 0) && (reg < kNumSimuRegisters));
   if (reg == 0)
     return 0;
   else
     return registers_[reg] + ((reg == pc) ? Instruction::kPCReadOffset : 0);
 }
 
 int32_t Simulator::get_fpu_register(int fpureg) const {
   ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters));
   return FPUregisters_[fpureg];
 }
 
 double Simulator::get_fpu_register_double(int fpureg) const {
   ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters) && ((fpureg % 2) == 0));
-  return *v8i::bit_cast<double*, int32_t*>(
+  return *v8i::BitCast<double*, int32_t*>(
       const_cast<int32_t*>(&FPUregisters_[fpureg]));
 }
 
 // Raw access to the PC register.
 void Simulator::set_pc(int32_t value) {
   pc_modified_ = true;
   registers_[pc] = value;
 }
 
 // Raw access to the PC register without the special adjustment when reading.
@@ skipping 255 matching lines @@
     case COP1:    // Coprocessor instructions
       switch (instr->RsFieldRaw()) {
         case BC1:   // branch on coprocessor condition
           UNREACHABLE();
           break;
         case MFC1:
           alu_out = get_fpu_register(fs_reg);
           break;
         case MFHC1:
           fp_out = get_fpu_register_double(fs_reg);
-          alu_out = *v8i::bit_cast<int32_t*, double*>(&fp_out);
+          alu_out = *v8i::BitCast<int32_t*, double*>(&fp_out);
           break;
         case MTC1:
         case MTHC1:
           // Do the store in the execution step.
           break;
         case S:
         case D:
         case W:
         case L:
         case PS:
@@ skipping 724 matching lines @@
   return address;
 }
 
 
 #undef UNSUPPORTED
 
 } }  // namespace assembler::mips
 
 #endif  // !defined(__mips)