Modify ARM .S code so it can be processed by both gnu-as and llvm-mc.

src/trusted/service_runtime/arch/arm/nacl_text_pad_test.S

Index: src/trusted/service_runtime/arch/arm/nacl_text_pad_test.S
===================================================================
--- src/trusted/service_runtime/arch/arm/nacl_text_pad_test.S	(revision 7372)
+++ src/trusted/service_runtime/arch/arm/nacl_text_pad_test.S	(working copy)
@@ -6,7 +6,9 @@
 #include "native_client/src/trusted/service_runtime/include/bits/nacl_syscalls.h"
 #include "native_client/src/trusted/service_runtime/nacl_config.h"
 
-        /*
+#define halt 0xe1266676
+
+/*

[jvoung - send to chromium..., 2011/12/07 18:39:02]

space to re-align the /*

[robertm, 2011/12/07 19:24:33]

Done.

          * Code to test various address layout boundary conditions.
          * This is a translation from the x86-{32,64} code, and is
          * not intended to be super efficent, just good enough to
@@ -14,8 +16,6 @@
          * strict control over the address space layout.
          */
 
-        .cpu cortex-a8

[jvoung - send to chromium..., 2011/12/07 18:39:02]

doesn't movw/movt require some cpu baseline?

Is this just something that wasn't added to the llvm arm asm parser yet?

[robertm, 2011/12/07 19:24:33]

llvm-mc does not like this pseudo and gnu-as does not miss it. We pass in
-mfpu=vfp -march=armv7-a through the command-line anyway.

On 2011/12/07 18:39:02, jvoung wrote:

-
         .text
 start_of_text:
         /*
@@ -64,8 +64,8 @@
         bne do_digit_16
 
         mov r1, r3
-        movw r3, #:lower16:NACL_SYSCALL_ADDR(NACL_sys_write)
-        movt r3, #:upper16:NACL_SYSCALL_ADDR(NACL_sys_write)
+        movw r3, :lower16:(NACL_SYSCALL_ADDR(NACL_sys_write))
+        movt r3, :upper16:(NACL_SYSCALL_ADDR(NACL_sys_write))
         nop
 
         nop
@@ -93,8 +93,8 @@
 
         mov r1, sp
         mov r2, #1
-        movw r3, #:lower16:NACL_SYSCALL_ADDR(NACL_sys_write)
-        movt r3, #:upper16:NACL_SYSCALL_ADDR(NACL_sys_write)
+        movw r3, :lower16:(NACL_SYSCALL_ADDR(NACL_sys_write))
+        movt r3, :upper16:(NACL_SYSCALL_ADDR(NACL_sys_write))
 
         nop
         nop
@@ -123,8 +123,8 @@
         nop
         bl write_char
 
-        movw r1, #:lower16:end_of_text
-        movt r1, #:upper16:end_of_text
+        movw r1, :lower16:(end_of_text)

[jvoung - send to chromium..., 2011/12/07 18:39:02]

Shouldn't there be a #? This could be a bug in the llvm asm parser?

Do you have an ARM reference that says the # is optional for these special
immediates? Almost every hit I see on google for arm lower16 syntax shows it
with the #. E.g., this one:

http://blogs.arm.com/software-enablement/251-how-to-load-constants-in-assembl...

[robertm, 2011/12/07 19:24:33]

gnu-as seems happy without it and llvm-mc dies not like it.
Also, note that :lower16: is not just merely a abbrev for
x & 0xffff but also forces a special relocation in case 
x is a symbol.
Bottom line: :lower16: is special enough that '#' might be implicit/optional


On 2011/12/07 18:39:02, jvoung wrote:

[jvoung - send to chromium..., 2011/12/07 20:32:12]

Sure, :lower16: is special and generates a relocation, but this may just be an
NYI on the llvm-mc front. If it is non-standard, perhaps file an LLVM bug -- it
may not take them too long to fix it...

+        movt r1, :upper16:(end_of_text)
         mov r0, #1
         bl write_num_16
 
@@ -134,8 +134,8 @@
         bl write_char
 
         mov r0, #0
-        movw r3, #:lower16:NACL_SYSCALL_ADDR(NACL_sys_sysbrk)
-        movt r3, #:upper16:NACL_SYSCALL_ADDR(NACL_sys_sysbrk)
+        movw r3, :lower16:(NACL_SYSCALL_ADDR(NACL_sys_sysbrk))
+        movt r3, :upper16:(NACL_SYSCALL_ADDR(NACL_sys_sysbrk))
         nop
 
         nop
@@ -154,8 +154,8 @@
         bl write_char
 
         mov r5, #0  /* r5 holds eventual exit status */
-        movw r1, #:lower16:EXPECTED_BREAK
-        movt r1, #:upper16:EXPECTED_BREAK
+        movw r1, :lower16:(EXPECTED_BREAK)
+        movt r1, :upper16:(EXPECTED_BREAK)
         cmp r1, r4
 
         movne r5, #1
@@ -170,17 +170,17 @@
 
 #if EXPECTED_RODATA != 0
         mov r2, #12
-        movw r1, #:lower16:ro_str
-        movt r1, #:upper16:ro_str
+        movw r1, :lower16:(ro_str)
+        movt r1, :upper16:(ro_str)
         mov r0, #1
 
-        movw r3, #:lower16:NACL_SYSCALL_ADDR(NACL_sys_write)
-        movt r3, #:upper16:NACL_SYSCALL_ADDR(NACL_sys_write)
+        movw r3, :lower16:(NACL_SYSCALL_ADDR(NACL_sys_write))
+        movt r3, :upper16:(NACL_SYSCALL_ADDR(NACL_sys_write))
         bic r3, r3, #0xc000000f
         blx r3
 
-        movw r1, #:lower16:ro_str
-        movt r1, #:upper16:ro_str
+        movw r1, :lower16:(ro_str)
+        movt r1, :upper16:(ro_str)
         mov r0, #1
         bl write_num_16
 
@@ -189,10 +189,10 @@
         nop
         bl write_char
 
-        movw r1, #:lower16:EXPECTED_RODATA
-        movt r1, #:upper16:EXPECTED_RODATA
-        movw r2, #:lower16:ro_str
-        movt r2, #:upper16:ro_str
+        movw r1, :lower16:(EXPECTED_RODATA)
+        movt r1, :upper16:(EXPECTED_RODATA)
+        movw r2, :lower16:(ro_str)
+        movt r2, :upper16:(ro_str)
 
         cmp r1, r2
         movne r5, #1
@@ -205,8 +205,8 @@
         bl write_char
 #endif
 
-        movw r3, #:lower16:NACL_SYSCALL_ADDR(NACL_sys_exit)
-        movt r3, #:upper16:NACL_SYSCALL_ADDR(NACL_sys_exit)
+        movw r3, :lower16:(NACL_SYSCALL_ADDR(NACL_sys_exit))
+        movt r3, :upper16:(NACL_SYSCALL_ADDR(NACL_sys_exit))
         mov r0, #0
         nop
 
@@ -214,9 +214,16 @@
         nop
         bic r3, r3, #0xc000000f
         blx r3
+#if defined(PNACL_AS)
+/* NOTE: unlike x86 the alignment directive on ARM takes
+   the logarithm of the alignment */
+#define POW2_BIGGER_THAN_DOT 14
+        .align32 POW2_BIGGER_THAN_DOT, halt
+        .fill (TEXT_EXTEND - (1 << POW2_BIGGER_THAN_DOT))/4, 4, halt
+#else
+        .fill (TEXT_EXTEND - (. - start_of_text))/4, 4, halt

[jvoung - send to chromium..., 2011/12/07 18:39:02]

is this workaround mostly because the llvm parser doesn't handle the feature
yet, or is it truly illegal?

[robertm, 2011/12/07 19:24:33]

This is just a NYI in the llvm asm parser/handler for arm.
I added similar hacks to the x86 siblings a while back.
There are few  comments in the llvm code that only a bare minimum has been
implemented, c.f. my updates to the bug tracker.

The assert mentioned in the description is likely also due to one of those NYI.
Apparently, some values given to :lower16: are not what llvm-mc expects. It does
not affect all values, though.



On 2011/12/07 18:39:02, jvoung wrote:

+#endif
 
-        /* use new proper halt */
-        .fill (TEXT_EXTEND - (. - start_of_text))/4, 4, 0xe1266676
 end_of_text:
 
 #if EXPECTED_RODATA != 0