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1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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102 { 0x8B, REG_OPER_OP_ORDER, "mov" }, | 102 { 0x8B, REG_OPER_OP_ORDER, "mov" }, |
103 { 0x8D, REG_OPER_OP_ORDER, "lea" }, | 103 { 0x8D, REG_OPER_OP_ORDER, "lea" }, |
104 { -1, UNSET_OP_ORDER, "" } | 104 { -1, UNSET_OP_ORDER, "" } |
105 }; | 105 }; |
106 | 106 |
107 | 107 |
108 static const ByteMnemonic zero_operands_instr[] = { | 108 static const ByteMnemonic zero_operands_instr[] = { |
109 { 0xC3, UNSET_OP_ORDER, "ret" }, | 109 { 0xC3, UNSET_OP_ORDER, "ret" }, |
110 { 0xC9, UNSET_OP_ORDER, "leave" }, | 110 { 0xC9, UNSET_OP_ORDER, "leave" }, |
111 { 0xF4, UNSET_OP_ORDER, "hlt" }, | 111 { 0xF4, UNSET_OP_ORDER, "hlt" }, |
| 112 { 0xFC, UNSET_OP_ORDER, "cld" }, |
112 { 0xCC, UNSET_OP_ORDER, "int3" }, | 113 { 0xCC, UNSET_OP_ORDER, "int3" }, |
113 { 0x60, UNSET_OP_ORDER, "pushad" }, | 114 { 0x60, UNSET_OP_ORDER, "pushad" }, |
114 { 0x61, UNSET_OP_ORDER, "popad" }, | 115 { 0x61, UNSET_OP_ORDER, "popad" }, |
115 { 0x9C, UNSET_OP_ORDER, "pushfd" }, | 116 { 0x9C, UNSET_OP_ORDER, "pushfd" }, |
116 { 0x9D, UNSET_OP_ORDER, "popfd" }, | 117 { 0x9D, UNSET_OP_ORDER, "popfd" }, |
117 { 0x9E, UNSET_OP_ORDER, "sahf" }, | 118 { 0x9E, UNSET_OP_ORDER, "sahf" }, |
118 { 0x99, UNSET_OP_ORDER, "cdq" }, | 119 { 0x99, UNSET_OP_ORDER, "cdq" }, |
119 { 0x9B, UNSET_OP_ORDER, "fwait" }, | 120 { 0x9B, UNSET_OP_ORDER, "fwait" }, |
120 { 0xA4, UNSET_OP_ORDER, "movs" }, | 121 { 0xA4, UNSET_OP_ORDER, "movs" }, |
121 { 0xA5, UNSET_OP_ORDER, "movs" }, | 122 { 0xA5, UNSET_OP_ORDER, "movs" }, |
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1027 // roundsd xmm, xmm/m64, imm8 | 1028 // roundsd xmm, xmm/m64, imm8 |
1028 AppendToBuffer("roundsd %s, ", NameOfCPURegister(regop)); | 1029 AppendToBuffer("roundsd %s, ", NameOfCPURegister(regop)); |
1029 current += PrintRightOperand(current); | 1030 current += PrintRightOperand(current); |
1030 AppendToBuffer(", %d", (*current) & 3); | 1031 AppendToBuffer(", %d", (*current) & 3); |
1031 current += 1; | 1032 current += 1; |
1032 } else { | 1033 } else { |
1033 UnimplementedInstruction(); | 1034 UnimplementedInstruction(); |
1034 } | 1035 } |
1035 } else { | 1036 } else { |
1036 get_modrm(*current, &mod, ®op, &rm); | 1037 get_modrm(*current, &mod, ®op, &rm); |
1037 if (opcode == 0x28) { | 1038 if (opcode == 0x1f) { |
| 1039 current++; |
| 1040 if (rm == 4) { // SIB byte present. |
| 1041 current++; |
| 1042 } |
| 1043 if (mod == 1) { // Byte displacement. |
| 1044 current += 1; |
| 1045 } else if (mod == 2) { // 32-bit displacement. |
| 1046 current += 4; |
| 1047 } // else no immediate displacement. |
| 1048 AppendToBuffer("nop"); |
| 1049 } else if (opcode == 0x28) { |
1038 AppendToBuffer("movapd %s, ", NameOfXMMRegister(regop)); | 1050 AppendToBuffer("movapd %s, ", NameOfXMMRegister(regop)); |
1039 current += PrintRightXMMOperand(current); | 1051 current += PrintRightXMMOperand(current); |
1040 } else if (opcode == 0x29) { | 1052 } else if (opcode == 0x29) { |
1041 AppendToBuffer("movapd "); | 1053 AppendToBuffer("movapd "); |
1042 current += PrintRightXMMOperand(current); | 1054 current += PrintRightXMMOperand(current); |
1043 AppendToBuffer(", %s", NameOfXMMRegister(regop)); | 1055 AppendToBuffer(", %s", NameOfXMMRegister(regop)); |
1044 } else if (opcode == 0x6E) { | 1056 } else if (opcode == 0x6E) { |
1045 AppendToBuffer("mov%c %s,", | 1057 AppendToBuffer("mov%c %s,", |
1046 rex_w() ? 'q' : 'd', | 1058 rex_w() ? 'q' : 'd', |
1047 NameOfXMMRegister(regop)); | 1059 NameOfXMMRegister(regop)); |
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1171 AppendToBuffer("movq %s, ", NameOfXMMRegister(regop)); | 1183 AppendToBuffer("movq %s, ", NameOfXMMRegister(regop)); |
1172 current += PrintRightXMMOperand(current); | 1184 current += PrintRightXMMOperand(current); |
1173 } else { | 1185 } else { |
1174 UnimplementedInstruction(); | 1186 UnimplementedInstruction(); |
1175 } | 1187 } |
1176 } else if (opcode == 0x1F) { | 1188 } else if (opcode == 0x1F) { |
1177 // NOP | 1189 // NOP |
1178 int mod, regop, rm; | 1190 int mod, regop, rm; |
1179 get_modrm(*current, &mod, ®op, &rm); | 1191 get_modrm(*current, &mod, ®op, &rm); |
1180 current++; | 1192 current++; |
1181 if (regop == 4) { // SIB byte present. | 1193 if (rm == 4) { // SIB byte present. |
1182 current++; | 1194 current++; |
1183 } | 1195 } |
1184 if (mod == 1) { // Byte displacement. | 1196 if (mod == 1) { // Byte displacement. |
1185 current += 1; | 1197 current += 1; |
1186 } else if (mod == 2) { // 32-bit displacement. | 1198 } else if (mod == 2) { // 32-bit displacement. |
1187 current += 4; | 1199 current += 4; |
1188 } // else no immediate displacement. | 1200 } // else no immediate displacement. |
1189 AppendToBuffer("nop"); | 1201 AppendToBuffer("nop"); |
1190 | 1202 |
1191 } else if (opcode == 0x28) { | 1203 } else if (opcode == 0x28) { |
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1825 for (int i = 6 - static_cast<int>(pc - prev_pc); i >= 0; i--) { | 1837 for (int i = 6 - static_cast<int>(pc - prev_pc); i >= 0; i--) { |
1826 fprintf(f, " "); | 1838 fprintf(f, " "); |
1827 } | 1839 } |
1828 fprintf(f, " %s\n", buffer.start()); | 1840 fprintf(f, " %s\n", buffer.start()); |
1829 } | 1841 } |
1830 } | 1842 } |
1831 | 1843 |
1832 } // namespace disasm | 1844 } // namespace disasm |
1833 | 1845 |
1834 #endif // V8_TARGET_ARCH_X64 | 1846 #endif // V8_TARGET_ARCH_X64 |
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