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Issue 8749002: Implement Math.pow using FPU instructions and inline it in crankshaft (ia32). (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Also do NaN/infinity check on base for TAGGED case. Created 9 years ago
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1 // Copyright 2011 the V8 project authors. All rights reserved. 1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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2565 EnsureSpace ensure_space(this); 2565 EnsureSpace ensure_space(this);
2566 emit(0x66); 2566 emit(0x66);
2567 emit_rex_64(dst, src); 2567 emit_rex_64(dst, src);
2568 emit(0x0F); 2568 emit(0x0F);
2569 emit(0x6F); 2569 emit(0x6F);
2570 emit_sse_operand(dst, src); 2570 emit_sse_operand(dst, src);
2571 } 2571 }
2572 2572
2573 2573
2574 void Assembler::extractps(Register dst, XMMRegister src, byte imm8) { 2574 void Assembler::extractps(Register dst, XMMRegister src, byte imm8) {
2575 ASSERT(is_uint2(imm8)); 2575 ASSERT(CpuFeatures::IsSupported(SSE4_1));
2576 ASSERT(is_uint8(imm8));
2576 EnsureSpace ensure_space(this); 2577 EnsureSpace ensure_space(this);
2577 emit(0x66); 2578 emit(0x66);
2578 emit_optional_rex_32(dst, src); 2579 emit_optional_rex_32(dst, src);
2579 emit(0x0F); 2580 emit(0x0F);
2580 emit(0x3A); 2581 emit(0x3A);
2581 emit(0x17); 2582 emit(0x17);
2582 emit_sse_operand(dst, src); 2583 emit_sse_operand(dst, src);
2583 emit(imm8); 2584 emit(imm8);
2584 } 2585 }
2585 2586
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3025 // specially coded on x64 means that it is a relative 32 bit address, as used 3026 // specially coded on x64 means that it is a relative 32 bit address, as used
3026 // by branch instructions. 3027 // by branch instructions.
3027 return (1 << rmode_) & kApplyMask; 3028 return (1 << rmode_) & kApplyMask;
3028 } 3029 }
3029 3030
3030 3031
3031 3032
3032 } } // namespace v8::internal 3033 } } // namespace v8::internal
3033 3034
3034 #endif // V8_TARGET_ARCH_X64 3035 #endif // V8_TARGET_ARCH_X64
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