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Issue 8520023: MIPS: Fix for Ins macro-assembler instruction for non-mips32r2 platforms. (Closed)
Patch Set: Created 9 years, 1 month ago
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1 // Copyright 2011 the V8 project authors. All rights reserved. 1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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903 } 903 }
904 } 904 }
905 } 905 }
906 906
907 907
908 void MacroAssembler::Ins(Register rt, 908 void MacroAssembler::Ins(Register rt,
909 Register rs, 909 Register rs,
910 uint16_t pos, 910 uint16_t pos,
911 uint16_t size) { 911 uint16_t size) {
912 ASSERT(pos < 32); 912 ASSERT(pos < 32);
913 ASSERT(pos + size < 32); 913 ASSERT(pos + size <= 32);
914 ASSERT(size != 0);
914 915
915 if (mips32r2) { 916 if (mips32r2) {
916 ins_(rt, rs, pos, size); 917 ins_(rt, rs, pos, size);
917 } else { 918 } else {
918 ASSERT(!rt.is(t8) && !rs.is(t8)); 919 ASSERT(!rt.is(t8) && !rs.is(t8));
919 920 Subu(at, zero_reg, Operand(1));
920 srl(t8, rt, pos + size); 921 srl(at, at, 32 - size);
921 // The left chunk from rt that needs to 922 and_(t8, rs, at);
922 // be saved is on the right side of t8. 923 sll(t8, t8, pos);
923 sll(at, t8, pos + size); 924 sll(at, at, pos);
924 // The 'at' register now contains the left chunk on 925 nor(at, at, zero_reg);
925 // the left (proper position) and zeroes. 926 and_(at, rt, at);
926 sll(t8, rt, 32 - pos); 927 or_(rt, t8, at);
927 // t8 now contains the right chunk on the left and zeroes.
928 srl(t8, t8, 32 - pos);
929 // t8 now contains the right chunk on
930 // the right (proper position) and zeroes.
931 or_(rt, at, t8);
932 // rt now contains the left and right chunks from the original rt
933 // in their proper position and zeroes in the middle.
934 sll(t8, rs, 32 - size);
935 // t8 now contains the chunk from rs on the left and zeroes.
936 srl(t8, t8, 32 - size - pos);
937 // t8 now contains the original chunk from rs in
938 // the middle (proper position).
939 or_(rt, rt, t8);
940 // rt now contains the result of the ins instruction in R2 mode.
941 } 928 }
942 } 929 }
943 930
944 931
945 void MacroAssembler::Cvt_d_uw(FPURegister fd, 932 void MacroAssembler::Cvt_d_uw(FPURegister fd,
946 FPURegister fs, 933 FPURegister fs,
947 FPURegister scratch) { 934 FPURegister scratch) {
948 // Move the data from fs to t8. 935 // Move the data from fs to t8.
949 mfc1(t8, fs); 936 mfc1(t8, fs);
950 Cvt_d_uw(fd, t8, scratch); 937 Cvt_d_uw(fd, t8, scratch);
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5044 opcode == BGTZL); 5031 opcode == BGTZL);
5045 opcode = (cond == eq) ? BEQ : BNE; 5032 opcode = (cond == eq) ? BEQ : BNE;
5046 instr = (instr & ~kOpcodeMask) | opcode; 5033 instr = (instr & ~kOpcodeMask) | opcode;
5047 masm_.emit(instr); 5034 masm_.emit(instr);
5048 } 5035 }
5049 5036
5050 5037
5051 } } // namespace v8::internal 5038 } } // namespace v8::internal
5052 5039
5053 #endif // V8_TARGET_ARCH_MIPS 5040 #endif // V8_TARGET_ARCH_MIPS
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