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| 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
| 2 // All Rights Reserved. | 2 // All Rights Reserved. |
| 3 // | 3 // |
| 4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
| 5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
| 6 // are met: | 6 // are met: |
| 7 // | 7 // |
| 8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
| 9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
| 10 // | 10 // |
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| 621 | 621 |
| 622 | 622 |
| 623 void Assembler::movzx_w(Register dst, const Operand& src) { | 623 void Assembler::movzx_w(Register dst, const Operand& src) { |
| 624 EnsureSpace ensure_space(this); | 624 EnsureSpace ensure_space(this); |
| 625 EMIT(0x0F); | 625 EMIT(0x0F); |
| 626 EMIT(0xB7); | 626 EMIT(0xB7); |
| 627 emit_operand(dst, src); | 627 emit_operand(dst, src); |
| 628 } | 628 } |
| 629 | 629 |
| 630 | 630 |
| 631 void Assembler::cmov(Condition cc, Register dst, int32_t imm32) { | |
| 632 ASSERT(CpuFeatures::IsEnabled(CMOV)); | |
| 633 EnsureSpace ensure_space(this); | |
| 634 UNIMPLEMENTED(); | |
| 635 USE(cc); | |
| 636 USE(dst); | |
| 637 USE(imm32); | |
| 638 } | |
| 639 | |
| 640 | |
| 641 void Assembler::cmov(Condition cc, Register dst, Handle<Object> handle) { | |
| 642 ASSERT(CpuFeatures::IsEnabled(CMOV)); | |
| 643 EnsureSpace ensure_space(this); | |
| 644 UNIMPLEMENTED(); | |
| 645 USE(cc); | |
| 646 USE(dst); | |
| 647 USE(handle); | |
| 648 } | |
| 649 | |
| 650 | |
| 651 void Assembler::cmov(Condition cc, Register dst, const Operand& src) { | 631 void Assembler::cmov(Condition cc, Register dst, const Operand& src) { |
| 652 ASSERT(CpuFeatures::IsEnabled(CMOV)); | 632 ASSERT(CpuFeatures::IsEnabled(CMOV)); |
| 653 EnsureSpace ensure_space(this); | 633 EnsureSpace ensure_space(this); |
| 654 // Opcode: 0f 40 + cc /r. | 634 // Opcode: 0f 40 + cc /r. |
| 655 EMIT(0x0F); | 635 EMIT(0x0F); |
| 656 EMIT(0x40 + cc); | 636 EMIT(0x40 + cc); |
| 657 emit_operand(dst, src); | 637 emit_operand(dst, src); |
| 658 } | 638 } |
| 659 | 639 |
| 660 | 640 |
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| 2506 fprintf(coverage_log, "%s\n", file_line); | 2486 fprintf(coverage_log, "%s\n", file_line); |
| 2507 fflush(coverage_log); | 2487 fflush(coverage_log); |
| 2508 } | 2488 } |
| 2509 } | 2489 } |
| 2510 | 2490 |
| 2511 #endif | 2491 #endif |
| 2512 | 2492 |
| 2513 } } // namespace v8::internal | 2493 } } // namespace v8::internal |
| 2514 | 2494 |
| 2515 #endif // V8_TARGET_ARCH_IA32 | 2495 #endif // V8_TARGET_ARCH_IA32 |
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