Chromium Code Reviews| Index: src/arm/macro-assembler-arm.h |
| diff --git a/src/arm/macro-assembler-arm.h b/src/arm/macro-assembler-arm.h |
| index 2222baaf975ea97ff2d93a2e69815fa572707724..90c4b375491c175f821966677a42ae2d08e32727 100644 |
| --- a/src/arm/macro-assembler-arm.h |
| +++ b/src/arm/macro-assembler-arm.h |
| @@ -320,8 +320,11 @@ class MacroAssembler: public Assembler { |
| } |
| // Push four registers. Pushes leftmost register first (to highest address). |
| - void Push(Register src1, Register src2, |
| - Register src3, Register src4, Condition cond = al) { |
| + void Push(Register src1, |
| + Register src2, |
| + Register src3, |
| + Register src4, |
| + Condition cond = al) { |
| ASSERT(!src1.is(src2)); |
| ASSERT(!src2.is(src3)); |
| ASSERT(!src1.is(src3)); |
| @@ -360,6 +363,57 @@ class MacroAssembler: public Assembler { |
| } |
| } |
|
Yang
2011/10/19 11:41:11
Not moving the function body to macro-assembler-ar
|
| + // Pop three registers. Pops rightmost register first (from lower address). |
| + void Pop(Register src1, Register src2, Register src3, Condition cond = al) { |
| + ASSERT(!src1.is(src2)); |
| + ASSERT(!src2.is(src3)); |
| + ASSERT(!src1.is(src3)); |
| + if (src1.code() > src2.code()) { |
| + if (src2.code() > src3.code()) { |
| + ldm(ia_w, sp, src1.bit() | src2.bit() | src3.bit(), cond); |
| + } else { |
| + ldr(src3, MemOperand(sp, 4, PostIndex), cond); |
| + ldm(ia_w, sp, src1.bit() | src2.bit(), cond); |
| + } |
| + } else { |
| + Pop(src2, src3, cond); |
| + str(src1, MemOperand(sp, 4, PostIndex), cond); |
| + } |
| + } |
| + |
| + // Pop four registers. Pops rightmost register first (from lower address). |
| + void Pop(Register src1, |
| + Register src2, |
| + Register src3, |
| + Register src4, |
| + Condition cond = al) { |
| + ASSERT(!src1.is(src2)); |
| + ASSERT(!src2.is(src3)); |
| + ASSERT(!src1.is(src3)); |
| + ASSERT(!src1.is(src4)); |
| + ASSERT(!src2.is(src4)); |
| + ASSERT(!src3.is(src4)); |
| + if (src1.code() > src2.code()) { |
| + if (src2.code() > src3.code()) { |
| + if (src3.code() > src4.code()) { |
| + ldm(ia_w, |
| + sp, |
| + src1.bit() | src2.bit() | src3.bit() | src4.bit(), |
| + cond); |
| + } else { |
| + ldr(src4, MemOperand(sp, 4, PostIndex), cond); |
| + ldm(ia_w, sp, src1.bit() | src2.bit() | src3.bit(), cond); |
| + } |
| + } else { |
| + Pop(src3, src4, cond); |
| + ldm(ia_w, sp, src1.bit() | src2.bit(), cond); |
| + } |
| + } else { |
| + Pop(src2, src3, src4, cond); |
| + ldr(src1, MemOperand(sp, 4, PostIndex), cond); |
| + } |
| + } |
| + |
| // Push and pop the registers that can hold pointers, as defined by the |
| // RegList constant kSafepointSavedRegisters. |
| void PushSafepointRegisters(); |