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1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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313 stm(db_w, sp, src1.bit() | src2.bit(), cond); | 313 stm(db_w, sp, src1.bit() | src2.bit(), cond); |
314 str(src3, MemOperand(sp, 4, NegPreIndex), cond); | 314 str(src3, MemOperand(sp, 4, NegPreIndex), cond); |
315 } | 315 } |
316 } else { | 316 } else { |
317 str(src1, MemOperand(sp, 4, NegPreIndex), cond); | 317 str(src1, MemOperand(sp, 4, NegPreIndex), cond); |
318 Push(src2, src3, cond); | 318 Push(src2, src3, cond); |
319 } | 319 } |
320 } | 320 } |
321 | 321 |
322 // Push four registers. Pushes leftmost register first (to highest address). | 322 // Push four registers. Pushes leftmost register first (to highest address). |
323 void Push(Register src1, Register src2, | 323 void Push(Register src1, |
324 Register src3, Register src4, Condition cond = al) { | 324 Register src2, |
325 Register src3, | |
326 Register src4, | |
327 Condition cond = al) { | |
325 ASSERT(!src1.is(src2)); | 328 ASSERT(!src1.is(src2)); |
326 ASSERT(!src2.is(src3)); | 329 ASSERT(!src2.is(src3)); |
327 ASSERT(!src1.is(src3)); | 330 ASSERT(!src1.is(src3)); |
328 ASSERT(!src1.is(src4)); | 331 ASSERT(!src1.is(src4)); |
329 ASSERT(!src2.is(src4)); | 332 ASSERT(!src2.is(src4)); |
330 ASSERT(!src3.is(src4)); | 333 ASSERT(!src3.is(src4)); |
331 if (src1.code() > src2.code()) { | 334 if (src1.code() > src2.code()) { |
332 if (src2.code() > src3.code()) { | 335 if (src2.code() > src3.code()) { |
333 if (src3.code() > src4.code()) { | 336 if (src3.code() > src4.code()) { |
334 stm(db_w, | 337 stm(db_w, |
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352 // Pop two registers. Pops rightmost register first (from lower address). | 355 // Pop two registers. Pops rightmost register first (from lower address). |
353 void Pop(Register src1, Register src2, Condition cond = al) { | 356 void Pop(Register src1, Register src2, Condition cond = al) { |
354 ASSERT(!src1.is(src2)); | 357 ASSERT(!src1.is(src2)); |
355 if (src1.code() > src2.code()) { | 358 if (src1.code() > src2.code()) { |
356 ldm(ia_w, sp, src1.bit() | src2.bit(), cond); | 359 ldm(ia_w, sp, src1.bit() | src2.bit(), cond); |
357 } else { | 360 } else { |
358 ldr(src2, MemOperand(sp, 4, PostIndex), cond); | 361 ldr(src2, MemOperand(sp, 4, PostIndex), cond); |
359 ldr(src1, MemOperand(sp, 4, PostIndex), cond); | 362 ldr(src1, MemOperand(sp, 4, PostIndex), cond); |
360 } | 363 } |
361 } | 364 } |
362 | 365 |
Yang
2011/10/19 11:41:11
Not moving the function body to macro-assembler-ar
| |
366 // Pop three registers. Pops rightmost register first (from lower address). | |
367 void Pop(Register src1, Register src2, Register src3, Condition cond = al) { | |
368 ASSERT(!src1.is(src2)); | |
369 ASSERT(!src2.is(src3)); | |
370 ASSERT(!src1.is(src3)); | |
371 if (src1.code() > src2.code()) { | |
372 if (src2.code() > src3.code()) { | |
373 ldm(ia_w, sp, src1.bit() | src2.bit() | src3.bit(), cond); | |
374 } else { | |
375 ldr(src3, MemOperand(sp, 4, PostIndex), cond); | |
376 ldm(ia_w, sp, src1.bit() | src2.bit(), cond); | |
377 } | |
378 } else { | |
379 Pop(src2, src3, cond); | |
380 str(src1, MemOperand(sp, 4, PostIndex), cond); | |
381 } | |
382 } | |
383 | |
384 // Pop four registers. Pops rightmost register first (from lower address). | |
385 void Pop(Register src1, | |
386 Register src2, | |
387 Register src3, | |
388 Register src4, | |
389 Condition cond = al) { | |
390 ASSERT(!src1.is(src2)); | |
391 ASSERT(!src2.is(src3)); | |
392 ASSERT(!src1.is(src3)); | |
393 ASSERT(!src1.is(src4)); | |
394 ASSERT(!src2.is(src4)); | |
395 ASSERT(!src3.is(src4)); | |
396 if (src1.code() > src2.code()) { | |
397 if (src2.code() > src3.code()) { | |
398 if (src3.code() > src4.code()) { | |
399 ldm(ia_w, | |
400 sp, | |
401 src1.bit() | src2.bit() | src3.bit() | src4.bit(), | |
402 cond); | |
403 } else { | |
404 ldr(src4, MemOperand(sp, 4, PostIndex), cond); | |
405 ldm(ia_w, sp, src1.bit() | src2.bit() | src3.bit(), cond); | |
406 } | |
407 } else { | |
408 Pop(src3, src4, cond); | |
409 ldm(ia_w, sp, src1.bit() | src2.bit(), cond); | |
410 } | |
411 } else { | |
412 Pop(src2, src3, src4, cond); | |
413 ldr(src1, MemOperand(sp, 4, PostIndex), cond); | |
414 } | |
415 } | |
416 | |
363 // Push and pop the registers that can hold pointers, as defined by the | 417 // Push and pop the registers that can hold pointers, as defined by the |
364 // RegList constant kSafepointSavedRegisters. | 418 // RegList constant kSafepointSavedRegisters. |
365 void PushSafepointRegisters(); | 419 void PushSafepointRegisters(); |
366 void PopSafepointRegisters(); | 420 void PopSafepointRegisters(); |
367 void PushSafepointRegistersAndDoubles(); | 421 void PushSafepointRegistersAndDoubles(); |
368 void PopSafepointRegistersAndDoubles(); | 422 void PopSafepointRegistersAndDoubles(); |
369 // Store value in register src in the safepoint stack slot for | 423 // Store value in register src in the safepoint stack slot for |
370 // register dst. | 424 // register dst. |
371 void StoreToSafepointRegisterSlot(Register src, Register dst); | 425 void StoreToSafepointRegisterSlot(Register src, Register dst); |
372 void StoreToSafepointRegistersAndDoublesSlot(Register src, Register dst); | 426 void StoreToSafepointRegistersAndDoublesSlot(Register src, Register dst); |
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1278 #define __FILE_LINE__ __FILE__ ":" CODE_COVERAGE_TOSTRING(__LINE__) | 1332 #define __FILE_LINE__ __FILE__ ":" CODE_COVERAGE_TOSTRING(__LINE__) |
1279 #define ACCESS_MASM(masm) masm->stop(__FILE_LINE__); masm-> | 1333 #define ACCESS_MASM(masm) masm->stop(__FILE_LINE__); masm-> |
1280 #else | 1334 #else |
1281 #define ACCESS_MASM(masm) masm-> | 1335 #define ACCESS_MASM(masm) masm-> |
1282 #endif | 1336 #endif |
1283 | 1337 |
1284 | 1338 |
1285 } } // namespace v8::internal | 1339 } } // namespace v8::internal |
1286 | 1340 |
1287 #endif // V8_ARM_MACRO_ASSEMBLER_ARM_H_ | 1341 #endif // V8_ARM_MACRO_ASSEMBLER_ARM_H_ |
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