Bugfix for r9690.

Bugfix for r9690.

BUG=arm debug test of mjsunit/elements-transition segfaults

Committed: http://code.google.com/p/v8/source/detail?r=9696

[Yang, 2011-10-19 10:00:05]

Bugfix for r9690. Please take a look.

http://codereview.chromium.org/8342032/diff/2001/src/arm/code-stubs-arm.cc
File src/arm/code-stubs-arm.cc (left):

http://codereview.chromium.org/8342032/diff/2001/src/arm/code-stubs-arm.cc#ol...
src/arm/code-stubs-arm.cc:7374: r3,
second register in RecordWrite is clobbered (in debug mode), therefore its value
has to be copied to a temp register first. Which also removes the need to use
pre-indexing trickery.

[Yang, 2011-10-19 10:10:48]

Take another look please. I changed the temp register from lr to r2 which is
also free.

[Sven Panne, 2011-10-19 10:43:34]

LGTM with a nit, which should probably be addressed in a separate CL

http://codereview.chromium.org/8342032/diff/3/src/arm/code-stubs-arm.cc
File src/arm/code-stubs-arm.cc (right):

http://codereview.chromium.org/8342032/diff/3/src/arm/code-stubs-arm.cc#newco...
src/arm/code-stubs-arm.cc:7391: __ Pop(r2, r3);
Not introduced by this CL, but anyway: Our ARM macro-assembler should really
have symmetrical push/pop instructions. Currently, we are able to push e.g. 4
registers in a single instruction, but pop only 2. Note that we have to be
careful with the argument order to get good code.