[MIPS] Initial support for MIPS architecture.

llvm/lib/Target/Mips/MipsTargetMachine.cpp

 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // Implements the info about Mips target spec.
@@ skipping 73 matching lines @@
   return false;
 }
 
 // Implemented by targets that want to run passes immediately before
 // machine code is emitted. return true if -print-machineinstrs should
 // print out the code after the passes.
 bool MipsTargetMachine::
 addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
 {
   PM.add(createMipsDelaySlotFillerPass(*this));
+
+  // @LOCALMOD-START
+  // This pass does all the heavy sfi lifting.
+  PM.add(createMipsNaClRewritePass());
+  // @LOCALMOD-END
+
   return true;
 }
 
 bool MipsTargetMachine::
 addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel) {
   // Do not restore $gp if target is Mips64.
   // In N32/64, $gp is a callee-saved register.
   if (!Subtarget.hasMips64())
     PM.add(createMipsEmitGPRestorePass(*this));
   return true;
 }
 
 bool MipsTargetMachine::
 addPostRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel) {
   PM.add(createMipsExpandPseudoPass(*this));
   return true;
 }
 
 bool MipsTargetMachine::addCodeEmitter(PassManagerBase &PM,
                                           CodeGenOpt::Level OptLevel,
                                           JITCodeEmitter &JCE) {
   // Machine code emitter pass for Mips.
   PM.add(createMipsJITCodeEmitterPass(*this, JCE));
   return false;
 }