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1 //===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===// | 1 //===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===// |
2 // | 2 // |
3 // The LLVM Compiler Infrastructure | 3 // The LLVM Compiler Infrastructure |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 // | 9 // |
10 // This file contains the MIPS implementation of the TargetRegisterInfo class. | 10 // This file contains the MIPS implementation of the TargetRegisterInfo class. |
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184 return N32CalleeSavedRegs; | 184 return N32CalleeSavedRegs; |
185 | 185 |
186 assert(Subtarget.isABI_N64()); | 186 assert(Subtarget.isABI_N64()); |
187 return N64CalleeSavedRegs; | 187 return N64CalleeSavedRegs; |
188 } | 188 } |
189 | 189 |
190 BitVector MipsRegisterInfo:: | 190 BitVector MipsRegisterInfo:: |
191 getReservedRegs(const MachineFunction &MF) const { | 191 getReservedRegs(const MachineFunction &MF) const { |
192 static const unsigned ReservedCPURegs[] = { | 192 static const unsigned ReservedCPURegs[] = { |
193 Mips::ZERO, Mips::AT, Mips::K0, Mips::K1, | 193 Mips::ZERO, Mips::AT, Mips::K0, Mips::K1, |
| 194 // @LOCALMOD-START |
| 195 Mips::IndirectBranchMaskReg, // Mips::T3 |
| 196 Mips::LoadStoreStackMaskReg, // Mips::T4 |
| 197 // @LOCALMOD-END |
194 Mips::GP, Mips::SP, Mips::FP, Mips::RA, 0 | 198 Mips::GP, Mips::SP, Mips::FP, Mips::RA, 0 |
195 }; | 199 }; |
196 | 200 |
197 static const unsigned ReservedCPU64Regs[] = { | 201 static const unsigned ReservedCPU64Regs[] = { |
198 Mips::ZERO_64, Mips::AT_64, Mips::K0_64, Mips::K1_64, | 202 Mips::ZERO_64, Mips::AT_64, Mips::K0_64, Mips::K1_64, |
199 Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64, 0 | 203 Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64, 0 |
200 }; | 204 }; |
201 | 205 |
202 BitVector Reserved(getNumRegs()); | 206 BitVector Reserved(getNumRegs()); |
203 typedef TargetRegisterClass::iterator RegIter; | 207 typedef TargetRegisterClass::iterator RegIter; |
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342 getEHExceptionRegister() const { | 346 getEHExceptionRegister() const { |
343 llvm_unreachable("What is the exception register"); | 347 llvm_unreachable("What is the exception register"); |
344 return 0; | 348 return 0; |
345 } | 349 } |
346 | 350 |
347 unsigned MipsRegisterInfo:: | 351 unsigned MipsRegisterInfo:: |
348 getEHHandlerRegister() const { | 352 getEHHandlerRegister() const { |
349 llvm_unreachable("What is the exception handler register"); | 353 llvm_unreachable("What is the exception handler register"); |
350 return 0; | 354 return 0; |
351 } | 355 } |
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