[MIPS] Initial support for MIPS architecture.

llvm/lib/Target/Mips/MipsRegisterInfo.cpp

 //===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the MIPS implementation of the TargetRegisterInfo class.
@@ skipping 173 matching lines @@
     return N32CalleeSavedRegs;
   
   assert(Subtarget.isABI_N64());
   return N64CalleeSavedRegs;  
 }
 
 BitVector MipsRegisterInfo::
 getReservedRegs(const MachineFunction &MF) const {
   static const unsigned ReservedCPURegs[] = {
     Mips::ZERO, Mips::AT, Mips::K0, Mips::K1, 
+    // @LOCALMOD-START
+    Mips::IndirectBranchMaskReg,  // Mips::T3
+    Mips::LoadStoreStackMaskReg,  // Mips::T4
+    // @LOCALMOD-END 
     Mips::GP, Mips::SP, Mips::FP, Mips::RA, 0
   };
 
   static const unsigned ReservedCPU64Regs[] = {
     Mips::ZERO_64, Mips::AT_64, Mips::K0_64, Mips::K1_64, 
     Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64, 0
   };
 
   BitVector Reserved(getNumRegs());
   typedef TargetRegisterClass::iterator RegIter;
@@ skipping 138 matching lines @@
 getEHExceptionRegister() const {
   llvm_unreachable("What is the exception register");
   return 0;
 }
 
 unsigned MipsRegisterInfo::
 getEHHandlerRegister() const {
   llvm_unreachable("What is the exception handler register");
   return 0;
 }