Speed up x86-64 validator by inlining heavily called routines. Speeds up

src/trusted/validator/x86/decoder/nc_inst_trans.c

 /*
  * Copyright (c) 2011 The Native Client Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /*
  * Translates the recognized opcode (instruction) in the instruction state
  * into an opcode expression.
  */
 
 #include "native_client/src/trusted/validator/x86/decoder/nc_inst_trans.h"
 
 #include <stdio.h>
 #include <assert.h>
 
 #include "native_client/src/shared/platform/nacl_log.h"
 #include "native_client/src/trusted/validator/x86/decoder/nc_inst_state.h"
 #include "native_client/src/trusted/validator/x86/decoder/nc_inst_state_internal.h"
+#include "native_client/src/trusted/validator/x86/decoder/ncopcode_desc_inl.h"
 #include "native_client/src/trusted/validator/x86/decoder/ncop_exps.h"
 #include "native_client/src/trusted/validator/x86/nacl_regs.h"
+#include "native_client/src/trusted/validator/x86/x86_insts_inl.h"
 
 #if NACL_TARGET_SUBARCH == 64
 # include "native_client/src/trusted/validator/x86/decoder/gen/nc_subregs_64.h"
 #else
 # include "native_client/src/trusted/validator/x86/decoder/gen/nc_subregs_32.h"
 #endif
 
 /* To turn on debugging of instruction decoding, change value of
  * DEBUGGING to 1.
  */
@@ skipping 46 matching lines @@
           return RegGS;
         default:
           break;
       }
     }
   }
   return reg_default;
 }
 
 /* Return the segment register to use if DS is the default. */
-static NaClOpKind NaClGetDsSegmentReg(NaClInstState* state) {
+static INLINE NaClOpKind NaClGetDsSegmentReg(NaClInstState* state) {
   return NaClGetSegmentPrefixReg(state, RegDS);
 }
 
 /* Return the segment register to use if ES is the default. */
-static NaClOpKind NaClGetEsSegmentReg(NaClInstState* state) {
+static INLINE NaClOpKind NaClGetEsSegmentReg(NaClInstState* state) {
   return NaClGetSegmentPrefixReg(state, RegES);
 }
 
 /* Append the given expression node onto the given vector of expression
  * nodes. Returns the appended expression node.
  */
-static NaClExp* NaClAppendExp(NaClExpKind kind,
-                              int32_t value,
-                              NaClExpFlags flags,
-                              NaClExpVector* vector) {
+static INLINE NaClExp* NaClAppendExp(NaClExpKind kind,
+                                     int32_t value,
+                                     NaClExpFlags flags,
+                                     NaClExpVector* vector) {
   NaClExp* node;
   assert(vector->number_expr_nodes < NACL_MAX_EXPS);
   node = &vector->node[vector->number_expr_nodes++];
   node->kind = kind;
   node->value = value;
   node->flags = flags;
   return node;
 }
 
 /* Report the given message and quit because we don't know
@@ skipping 42 matching lines @@
   }
   NaClFatal("Unable to determine segment regsiter from instruction name",
             state);
   /* NOT REACHED */
   return RegUnknown;
 }
 
 /* Append the given constant onto the given vector of expression
  * nodes. Returns the appended expression node.
  */
-static NaClExp* NaClAppendConst(uint64_t value, NaClExpFlags flags,
-                                NaClExpVector* vector) {
+static INLINE NaClExp* NaClAppendConst(uint64_t value, NaClExpFlags flags,
+                                       NaClExpVector* vector) {
   uint32_t val1;
   uint32_t val2;
   DEBUG(
       NaClLog(LOG_INFO, "Append constant %"NACL_PRIx64" : ", value);
       NaClPrintExpFlags(NaClLogGetGio(), flags);
       gprintf(NaClLogGetGio(), "\n"));
   NaClSplitExpConstant(value, &val1, &val2);
   if (val2 == 0) {
     return NaClAppendExp(ExprConstant, val1, flags, vector);
   } else {
@@ skipping 282 matching lines @@
   case RegR15:
     return NACL_EFLAG(ExprSize64);
   default:
     return 0;
   }
 }
 
 /* Appends the given kind of register onto the vector of expression nodes.
  * Returns the appended register.
  */
-static NaClExp* NaClAppendReg(NaClOpKind r, NaClExpVector* vector) {
+static INLINE NaClExp* NaClAppendReg(NaClOpKind r, NaClExpVector* vector) {
   NaClExp* node;
   DEBUG(NaClLog(LOG_INFO, "append register %s\n", NaClOpKindName(r)));
   node = NaClAppendExp(ExprRegister, r, NaClGetRegSize(r), vector);
   DEBUG(NaClExpVectorPrint(NaClLogGetGio(), vector));
   return node;
 }
 
 /* Given the given register kind, and the corresponding index, append
  * the appropriate register onto the vector of expression nodes.
  * Returns the appended register
  */
-static NaClExp* NaClAppendRegKind(NaClInstState* state,
-                                  NaClRegKind kind, int reg_index) {
+static INLINE NaClExp* NaClAppendRegKind(NaClInstState* state,
+                                         NaClRegKind kind, int reg_index) {
   DEBUG(NaClLog(LOG_INFO, "NaClAppendRegKind(%d, %d) = %s\n",
                 (int) kind, reg_index, NaClRegKindName(kind)));
   return NaClAppendReg(NaClLookupReg(state, kind, reg_index), &state->nodes);
 }
 
 /* Given an operand of the corresponding opcode instruction of the
  * given state, return what kind of register should be used, based
  * on the operand size.
  */
 static NaClRegKind NaClExtractOpRegKind(NaClInstState* state,
@@ skipping 25 matching lines @@
         return RegSize64;
       } else {
         return RegSize32;
       }
   }
 }
 
 /* Given an address of the corresponding opcode instruction of the
  * given state, return what kind of register should be used.
  */
-static NaClRegKind NaClExtractAddressRegKind(NaClInstState* state) {
+static INLINE NaClRegKind NaClExtractAddressRegKind(NaClInstState* state) {
   if (state->address_size == 16) {
     return RegSize16;
   } else if (state->address_size == 64) {
     return RegSize64;
   } else {
     return RegSize32;
   }
 }
 
 /* Given we want to translate an operand (of the form G_Operand),
@@ skipping 62 matching lines @@
     RegES,
     RegCS,
     RegSS,
     RegDS,
     RegFS,
     RegGS,
     /* These should not happen. */
     RegUnknown,
     RegUnknown
   };
-  return NaClAppendReg(seg[modrm_reg(state->modrm)], &state->nodes);
+  return NaClAppendReg(seg[modrm_regInline(state->modrm)], &state->nodes);
 }
 
 /* For the given instruction state, and the corresponding 3-bit specification
  * of a register, update it to a 4-bit specification, based on the REX.R bit.
  */
-static int NaClGetRexRReg(NaClInstState* state, int reg) {
+static INLINE int NaClGetRexRReg(NaClInstState* state, int reg) {
   DEBUG(NaClLog(LOG_INFO, "Get GenRexRRegister %d\n", reg));
   if (NACL_TARGET_SUBARCH == 64 && (state->rexprefix & 0x4)) {
     reg += 8;
   }
   return reg;
 }
 
 /* For the given instruction state, and the corresponding 3-bit specification
  * of a register, update it to a 4-bit specification, based on the REX.X bit.
  */
-static int NaClGetRexXReg(NaClInstState* state, int reg) {
+static INLINE int NaClGetRexXReg(NaClInstState* state, int reg) {
   DEBUG(NaClLog(LOG_INFO, "Get GenRexXRegister\n"));
   if (NACL_TARGET_SUBARCH == 64 && (state->rexprefix & 0x2)) {
     reg += 8;
   }
   return reg;
 }
 
 /* For the given instruction state, and the corresponding 3-bit specification
  * of a register, update it to a 4-bit specification, based on the REX.B bit.
  */
-static int NaClGetRexBReg(NaClInstState* state, int reg) {
+static INLINE int NaClGetRexBReg(NaClInstState* state, int reg) {
   DEBUG(NaClLog(LOG_INFO, "Get GenRexBRegister\n"));
   if (NACL_TARGET_SUBARCH == 64 && (state->rexprefix & 0x1)) {
     DEBUG(NaClLog(LOG_INFO, "rexprefix == %02x\n", state->rexprefix));
     reg += 8;
   }
   return reg;
 }
 
 /* Return the general purpose register associated with the modrm.reg
  * field.
  */
-static int NaClGetGenRegRegister(NaClInstState* state) {
+static INLINE int NaClGetGenRegRegister(NaClInstState* state) {
   DEBUG(NaClLog(LOG_INFO, "Get GenRegRegister\n"));
-  return NaClGetRexRReg(state, modrm_reg(state->modrm));
+  return NaClGetRexRReg(state, modrm_regInline(state->modrm));
 }
 
 /* Return the general purpose register associated with the modrm.rm
  * field.
  */
-static int NaClGetGenRmRegister(NaClInstState* state) {
+static INLINE int NaClGetGenRmRegister(NaClInstState* state) {
   DEBUG(NaClLog(LOG_INFO, "Get GenRmRegister\n"));
-  return NaClGetRexBReg(state, modrm_rm(state->modrm));
+  return NaClGetRexBReg(state, modrm_rmInline(state->modrm));
 }
 
 /* Get the register index from the difference of the opcode, and
  * its opcode base.
  */
 static NaClExp* NaClAppendOpcodeBaseReg(
     NaClInstState* state, const NaClOp* operand) {
   int reg_index;
   reg_index = NaClGetOpcodePlusR(state->inst->opcode_ext);
   assert(reg_index >= 0 && reg_index < 8);
@@ skipping 12 matching lines @@
   DEBUG(NaClLog(LOG_INFO, "Translate opcode base register %d\n", reg_index));
   return NaClAppendReg(RegST0 + reg_index, &state->nodes);
 }
 
 /* Model the extraction of a displacement value and the associated flags. */
 typedef struct NaClDisplacement {
   uint64_t value;
   NaClExpFlags flags;
 } NaClDisplacement;
 
-static void NaClInitializeDisplacement(uint64_t value, NaClExpFlags flags,
-                                       NaClDisplacement* displacement) {
+static INLINE void NaClInitializeDisplacement(
+    uint64_t value, NaClExpFlags flags,
+    NaClDisplacement* displacement) {
   displacement->value = value;
   displacement->flags = flags;
 }
 
 /* Extract the binary value from the specified bytes of the instruction. */
 uint64_t NaClExtractUnsignedBinaryValue(NaClInstState* state,
                                         int start_byte, int num_bytes) {
   int i;
   uint64_t value = 0;
   for (i = 0; i < num_bytes; ++i) {
@@ skipping 277 matching lines @@
   DEBUG(NaClLog(LOG_INFO, "finished appending memory offset:\n"));
   DEBUG(NaClExpVectorPrint(NaClLogGetGio(), &state->nodes));
   return root;
 }
 
 /* Extract the base register from the SIB byte. */
 static NaClOpKind NaClGetSibBase(NaClInstState* state) {
   int base = sib_base(state->sib);
   NaClOpKind base_reg = RegUnknown;
   if (0x5 == base) {
-    switch (modrm_mod(state->modrm)) {
+    switch (modrm_modInline(state->modrm)) {
       case 0:
         break;
       case 1:
       case 2:
         if (NACL_TARGET_SUBARCH == 64) {
           if (state->rexprefix & 0x1) {
             base_reg = RegR13;
           } else {
             base_reg = RegRBP;
           }
@@ skipping 105 matching lines @@
 
 /* Get the Effective address in the mod/rm byte, if the modrm.mod field
  * is 00, and append it to the vector of expression nodes. Operand is
  * the corresponding operand of the opcode associated with the instruction
  * of the given state that corresponds to the effective address. Returns
  * the root of the appended effective address.
  */
 static NaClExp* NaClAppendMod00EffectiveAddress(
     NaClInstState* state, const NaClOp* operand) {
   DEBUG(NaClLog(LOG_INFO, "Translate modrm(%02x).mod == 00\n", state->modrm));
-  switch (modrm_rm(state->modrm)) {
+  switch (modrm_rmInline(state->modrm)) {
     case 4:
       return NaClAppendSib(state);
     case 5:
       if (NACL_TARGET_SUBARCH == 64) {
         NaClDisplacement displacement;
         NaClExtractDisplacement(state, &displacement,
                                 NACL_EFLAG(ExprSignedHex));
         return NaClAppendMemoryOffset(state,
                                       RegRIP,
                                       RegUnknown,
@@ skipping 21 matching lines @@
 
 /* Get the Effective address in the mod/rm byte, if the modrm.mod field
  * is 01, and append it to the vector of expression nodes. Operand is
  * the corresponding operand of the opcode associated with the instruction
  * of the given state that corresponds to the effective address. Returns
  * the root of the appended effective address.
  */
 static NaClExp* NaClAppendMod01EffectiveAddress(
     NaClInstState* state, const NaClOp* operand) {
   DEBUG(NaClLog(LOG_INFO, "Translate modrm(%02x).mod == 01\n", state->modrm));
-  if (4 == modrm_rm(state->modrm)) {
+  if (4 == modrm_rmInline(state->modrm)) {
     return NaClAppendSib(state);
   } else {
     NaClDisplacement displacement;
     NaClExtractDisplacement(state, &displacement, NACL_EFLAG(ExprSignedHex));
     return NaClAppendMemoryOffset(state,
                                   NaClLookupReg(
                                       state,
                                       NaClExtractAddressRegKind(state),
                                       NaClGetGenRmRegister(state)),
                                   RegUnknown,
                                   1,
                                   &displacement);
   }
 }
 
 /* Get the Effective address in the mod/rm byte, if the modrm.mod field
  * is 10, and append it to the vector of expression nodes. Operand is
  * the corresponding operand of the opcode associated with the instruction
  * of the given state that corresponds to the effective address. Returns
  * the root of the appended effective address.
  */
 static NaClExp* NaClAppendMod10EffectiveAddress(
     NaClInstState* state, const NaClOp* operand) {
   DEBUG(NaClLog(LOG_INFO, "Translate modrm(%02x).mod == 10\n", state->modrm));
-  if (4 == modrm_rm(state->modrm)) {
+  if (4 == modrm_rmInline(state->modrm)) {
     return NaClAppendSib(state);
   } else {
     NaClDisplacement displacement;
     NaClOpKind base =
         NaClLookupReg(state,
                       NaClExtractAddressRegKind(state),
                       NaClGetGenRmRegister(state));
     NaClExtractDisplacement(state, &displacement, NACL_EFLAG(ExprSignedHex));
     return NaClAppendMemoryOffset(state, base, RegUnknown, 1, &displacement);
   }
@@ skipping 46 matching lines @@
     default:
       return NaClFatal("can't translate register group: address size not valid",
                        state);
   }
 }
 
 /* Compute the effect address using the Mod/Rm and SIB bytes. */
 static NaClExp* NaClAppendEffectiveAddress(
     NaClInstState* state, const NaClOp* operand,
     NaClModRmRegKind modrm_reg_kind) {
-  switch(modrm_mod(state->modrm)) {
+  switch(modrm_modInline(state->modrm)) {
     case 0:
       return NaClAppendMod00EffectiveAddress(state, operand);
     case 1:
       return NaClAppendMod01EffectiveAddress(state, operand);
     case 2:
       return NaClAppendMod10EffectiveAddress(state, operand);
     case 3:
       return NaClAppendMod11EffectiveAddress(state, operand, modrm_reg_kind);
     default:
       break;
@@ skipping 291 matching lines @@
   if (operand->flags & NACL_OPFLAG(OpUse)) {
     node->flags |= NACL_EFLAG(ExprUsed);
   }
   if (operand->flags & NACL_OPFLAG(OpAddress)) {
     node->flags |= NACL_EFLAG(ExprAddress);
   }
   return node;
 }
 
 void NaClBuildExpVector(struct NaClInstState* state) {
-  int i;
+  uint8_t i;
+  uint8_t num_ops;
   DEBUG(NaClLog(LOG_INFO,
                 "building expression vector for pc = %"NACL_PRIxNaClPcAddress
                 ":\n",
                 NaClInstStateVpc(state)));
-  for (i = 0; i < state->inst->num_operands; i++) {
+  num_ops = NaClGetInstNumberOperandsInline(state->inst);
+  for (i = 0; i < num_ops; i++) {
     NaClExp* n;
-    const NaClOp* op = NaClGetInstOperand(state->decoder_tables,
-                                          state->inst, i);
+    const NaClOp* op = NaClGetInstOperandInline(state->decoder_tables,
+                                                state->inst, i);
     DEBUG(NaClLog(LOG_INFO, "translating operand %d:\n", i));
     n = NaClAppendExp(OperandReference, i, 0, &state->nodes);
     if (op->flags & NACL_OPFLAG(OpImplicit)) {
       n->flags |= NACL_EFLAG(ExprImplicit);
     }
     NaClAddOpSetUse(NaClAppendOperand(state, op), op);
     DEBUG(NaClExpVectorPrint(NaClLogGetGio(), &state->nodes));
   }
 }