MIPS: Fix assertion-fail on cacheflush from generated code.

src/mips/macro-assembler-mips.cc

Index: src/mips/macro-assembler-mips.cc
diff --git a/src/mips/macro-assembler-mips.cc b/src/mips/macro-assembler-mips.cc
index be5c9bd300d5ed8200e475035701d8fbf8267365..b3ff82a17777062e6f5cb3db18961a6665575b5b 100644
--- a/src/mips/macro-assembler-mips.cc
+++ b/src/mips/macro-assembler-mips.cc
@@ -821,6 +821,7 @@ void MacroAssembler::MultiPopReversedFPU(RegList regs) {
 void MacroAssembler::FlushICache(Register address, unsigned instructions) {
   RegList saved_regs = kJSCallerSaved | ra.bit();
   MultiPush(saved_regs);
+  AllowExternalCallThatCantCauseGC scope(this);
 
   // Save to a0 in case address == t0.
   Move(a0, address);