MIPS: pre-crankshaft updates to assembler and related files. (1/3)

src/mips/constants-mips.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 173 matching lines @@
     default:
       return false;
   };
 }
 
 
 bool Instruction::IsLinkingInstruction() const {
   const int op = OpcodeFieldRaw();
   switch (op) {
     case JAL:
+      return true;
     case REGIMM:
       switch (RtFieldRaw()) {
         case BGEZAL:
         case BLTZAL:
           return true;
       default:
         return false;
       };
     case SPECIAL:
       switch (FunctionFieldRaw()) {
@@ skipping 61 matching lines @@
         case TGEU:
         case TLT:
         case TLTU:
         case TEQ:
         case TNE:
         case MOVZ:
         case MOVN:
         case MOVCI:
           return kRegisterType;
         default:
-          UNREACHABLE();
+          return kUnsupported;
       };
       break;
     case SPECIAL2:
       switch (FunctionFieldRaw()) {
         case MUL:
         case CLZ:
           return kRegisterType;
         default:
-          UNREACHABLE();
+          return kUnsupported;
       };
       break;
     case SPECIAL3:
       switch (FunctionFieldRaw()) {
         case INS:
         case EXT:
           return kRegisterType;
         default:
-          UNREACHABLE();
+          return kUnsupported;
       };
       break;
     case COP1:    // Coprocessor instructions.
       switch (RsFieldRawNoAssert()) {
         case BC1:   // Branch on coprocessor condition.
           return kImmediateType;
         default:
           return kRegisterType;
       };
       break;
@@ skipping 30 matching lines @@
     case LWC1:
     case LDC1:
     case SWC1:
     case SDC1:
       return kImmediateType;
     // 26 bits immediate type instructions. eg: j imm26.
     case J:
     case JAL:
       return kJumpType;
     default:
-      UNREACHABLE();
+      return kUnsupported;
   };
   return kUnsupported;
 }
 
 
 } }   // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_MIPS