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Issue 7834034: Clean up RegOp2MemOp tables in X86InstrInfo.cpp (Closed) Base URL: http://llvm.org/svn/llvm-project/llvm/trunk/
Patch Set: x Created 9 years, 3 months ago
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1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===// 1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
2 // 2 //
3 // The LLVM Compiler Infrastructure 3 // The LLVM Compiler Infrastructure
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class. 10 // This file contains the X86 implementation of the TargetInstrInfo class.
(...skipping 35 matching lines...) Expand 10 before | Expand all | Expand 10 after
46 static cl::opt<bool> 46 static cl::opt<bool>
47 PrintFailedFusing("print-failed-fuse-candidates", 47 PrintFailedFusing("print-failed-fuse-candidates",
48 cl::desc("Print instructions that the allocator wants to" 48 cl::desc("Print instructions that the allocator wants to"
49 " fuse, but the X86 backend currently can't"), 49 " fuse, but the X86 backend currently can't"),
50 cl::Hidden); 50 cl::Hidden);
51 static cl::opt<bool> 51 static cl::opt<bool>
52 ReMatPICStubLoad("remat-pic-stub-load", 52 ReMatPICStubLoad("remat-pic-stub-load",
53 cl::desc("Re-materialize load from stub in PIC mode"), 53 cl::desc("Re-materialize load from stub in PIC mode"),
54 cl::init(false), cl::Hidden); 54 cl::init(false), cl::Hidden);
55 55
56 enum {
57 TB_INDEX_0 = 0,
58 TB_INDEX_1 = 1,
59 TB_INDEX_2 = 2,
60 TB_INDEX_MASK = 0xff,
61
62 TB_ALIGN_SHIFT = 8,
63 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT,
64 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT,
65 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT,
66 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT,
67
68 // Do not insert the reverse map (MemOp -> RegOp) into the table.
69 // This may be needed because there is a many -> one mapping.
70 TB_NO_REVERSE = 1 << 16,
71
72 // Do not insert the forward map (RegOp -> MemOp) into the table.
73 // This is needed for Native Client, which prohibits branch
74 // instructions from using a memory operand.
75 TB_NO_FORWARD = 1 << 17,
76
77 TB_FOLDED_LOAD = 1 << 18,
78 TB_FOLDED_STORE = 1 << 19
79 };
80
56 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) 81 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
57 : X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit() 82 : X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit()
58 ? X86::ADJCALLSTACKDOWN64 83 ? X86::ADJCALLSTACKDOWN64
59 : X86::ADJCALLSTACKDOWN32), 84 : X86::ADJCALLSTACKDOWN32),
60 (tm.getSubtarget<X86Subtarget>().is64Bit() 85 (tm.getSubtarget<X86Subtarget>().is64Bit()
61 ? X86::ADJCALLSTACKUP64 86 ? X86::ADJCALLSTACKUP64
62 : X86::ADJCALLSTACKUP32)), 87 : X86::ADJCALLSTACKUP32)),
63 TM(tm), RI(tm, *this) { 88 TM(tm), RI(tm, *this) {
64 enum { 89
65 TB_NOT_REVERSABLE = 1U << 31, 90 static const unsigned OpTbl2Addr[][3] = {
66 TB_FLAGS = TB_NOT_REVERSABLE 91 { X86::ADC32ri, X86::ADC32mi, 0 },
67 }; 92 { X86::ADC32ri8, X86::ADC32mi8, 0 },
68 93 { X86::ADC32rr, X86::ADC32mr, 0 },
69 static const unsigned OpTbl2Addr[][2] = { 94 { X86::ADC64ri32, X86::ADC64mi32, 0 },
70 { X86::ADC32ri, X86::ADC32mi }, 95 { X86::ADC64ri8, X86::ADC64mi8, 0 },
71 { X86::ADC32ri8, X86::ADC32mi8 }, 96 { X86::ADC64rr, X86::ADC64mr, 0 },
72 { X86::ADC32rr, X86::ADC32mr }, 97 { X86::ADD16ri, X86::ADD16mi, 0 },
73 { X86::ADC64ri32, X86::ADC64mi32 }, 98 { X86::ADD16ri8, X86::ADD16mi8, 0 },
74 { X86::ADC64ri8, X86::ADC64mi8 }, 99 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
75 { X86::ADC64rr, X86::ADC64mr }, 100 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
76 { X86::ADD16ri, X86::ADD16mi }, 101 { X86::ADD16rr, X86::ADD16mr, 0 },
77 { X86::ADD16ri8, X86::ADD16mi8 }, 102 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
78 { X86::ADD16ri_DB, X86::ADD16mi | TB_NOT_REVERSABLE }, 103 { X86::ADD32ri, X86::ADD32mi, 0 },
79 { X86::ADD16ri8_DB, X86::ADD16mi8 | TB_NOT_REVERSABLE }, 104 { X86::ADD32ri8, X86::ADD32mi8, 0 },
80 { X86::ADD16rr, X86::ADD16mr }, 105 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
81 { X86::ADD16rr_DB, X86::ADD16mr | TB_NOT_REVERSABLE }, 106 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
82 { X86::ADD32ri, X86::ADD32mi }, 107 { X86::ADD32rr, X86::ADD32mr, 0 },
83 { X86::ADD32ri8, X86::ADD32mi8 }, 108 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
84 { X86::ADD32ri_DB, X86::ADD32mi | TB_NOT_REVERSABLE }, 109 { X86::ADD64ri32, X86::ADD64mi32, 0 },
85 { X86::ADD32ri8_DB, X86::ADD32mi8 | TB_NOT_REVERSABLE }, 110 { X86::ADD64ri8, X86::ADD64mi8, 0 },
86 { X86::ADD32rr, X86::ADD32mr }, 111 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
87 { X86::ADD32rr_DB, X86::ADD32mr | TB_NOT_REVERSABLE }, 112 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
88 { X86::ADD64ri32, X86::ADD64mi32 }, 113 { X86::ADD64rr, X86::ADD64mr, 0 },
89 { X86::ADD64ri8, X86::ADD64mi8 }, 114 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
90 { X86::ADD64ri32_DB,X86::ADD64mi32 | TB_NOT_REVERSABLE }, 115 { X86::ADD8ri, X86::ADD8mi, 0 },
91 { X86::ADD64ri8_DB, X86::ADD64mi8 | TB_NOT_REVERSABLE }, 116 { X86::ADD8rr, X86::ADD8mr, 0 },
92 { X86::ADD64rr, X86::ADD64mr }, 117 { X86::AND16ri, X86::AND16mi, 0 },
93 { X86::ADD64rr_DB, X86::ADD64mr | TB_NOT_REVERSABLE }, 118 { X86::AND16ri8, X86::AND16mi8, 0 },
94 { X86::ADD8ri, X86::ADD8mi }, 119 { X86::AND16rr, X86::AND16mr, 0 },
95 { X86::ADD8rr, X86::ADD8mr }, 120 { X86::AND32ri, X86::AND32mi, 0 },
96 { X86::AND16ri, X86::AND16mi }, 121 { X86::AND32ri8, X86::AND32mi8, 0 },
97 { X86::AND16ri8, X86::AND16mi8 }, 122 { X86::AND32rr, X86::AND32mr, 0 },
98 { X86::AND16rr, X86::AND16mr }, 123 { X86::AND64ri32, X86::AND64mi32, 0 },
99 { X86::AND32ri, X86::AND32mi }, 124 { X86::AND64ri8, X86::AND64mi8, 0 },
100 { X86::AND32ri8, X86::AND32mi8 }, 125 { X86::AND64rr, X86::AND64mr, 0 },
101 { X86::AND32rr, X86::AND32mr }, 126 { X86::AND8ri, X86::AND8mi, 0 },
102 { X86::AND64ri32, X86::AND64mi32 }, 127 { X86::AND8rr, X86::AND8mr, 0 },
103 { X86::AND64ri8, X86::AND64mi8 }, 128 { X86::DEC16r, X86::DEC16m, 0 },
104 { X86::AND64rr, X86::AND64mr }, 129 { X86::DEC32r, X86::DEC32m, 0 },
105 { X86::AND8ri, X86::AND8mi }, 130 { X86::DEC64_16r, X86::DEC64_16m, 0 },
106 { X86::AND8rr, X86::AND8mr }, 131 { X86::DEC64_32r, X86::DEC64_32m, 0 },
107 { X86::DEC16r, X86::DEC16m }, 132 { X86::DEC64r, X86::DEC64m, 0 },
108 { X86::DEC32r, X86::DEC32m }, 133 { X86::DEC8r, X86::DEC8m, 0 },
109 { X86::DEC64_16r, X86::DEC64_16m }, 134 { X86::INC16r, X86::INC16m, 0 },
110 { X86::DEC64_32r, X86::DEC64_32m }, 135 { X86::INC32r, X86::INC32m, 0 },
111 { X86::DEC64r, X86::DEC64m }, 136 { X86::INC64_16r, X86::INC64_16m, 0 },
112 { X86::DEC8r, X86::DEC8m }, 137 { X86::INC64_32r, X86::INC64_32m, 0 },
113 { X86::INC16r, X86::INC16m }, 138 { X86::INC64r, X86::INC64m, 0 },
114 { X86::INC32r, X86::INC32m }, 139 { X86::INC8r, X86::INC8m, 0 },
115 { X86::INC64_16r, X86::INC64_16m }, 140 { X86::NEG16r, X86::NEG16m, 0 },
116 { X86::INC64_32r, X86::INC64_32m }, 141 { X86::NEG32r, X86::NEG32m, 0 },
117 { X86::INC64r, X86::INC64m }, 142 { X86::NEG64r, X86::NEG64m, 0 },
118 { X86::INC8r, X86::INC8m }, 143 { X86::NEG8r, X86::NEG8m, 0 },
119 { X86::NEG16r, X86::NEG16m }, 144 { X86::NOT16r, X86::NOT16m, 0 },
120 { X86::NEG32r, X86::NEG32m }, 145 { X86::NOT32r, X86::NOT32m, 0 },
121 { X86::NEG64r, X86::NEG64m }, 146 { X86::NOT64r, X86::NOT64m, 0 },
122 { X86::NEG8r, X86::NEG8m }, 147 { X86::NOT8r, X86::NOT8m, 0 },
123 { X86::NOT16r, X86::NOT16m }, 148 { X86::OR16ri, X86::OR16mi, 0 },
124 { X86::NOT32r, X86::NOT32m }, 149 { X86::OR16ri8, X86::OR16mi8, 0 },
125 { X86::NOT64r, X86::NOT64m }, 150 { X86::OR16rr, X86::OR16mr, 0 },
126 { X86::NOT8r, X86::NOT8m }, 151 { X86::OR32ri, X86::OR32mi, 0 },
127 { X86::OR16ri, X86::OR16mi }, 152 { X86::OR32ri8, X86::OR32mi8, 0 },
128 { X86::OR16ri8, X86::OR16mi8 }, 153 { X86::OR32rr, X86::OR32mr, 0 },
129 { X86::OR16rr, X86::OR16mr }, 154 { X86::OR64ri32, X86::OR64mi32, 0 },
130 { X86::OR32ri, X86::OR32mi }, 155 { X86::OR64ri8, X86::OR64mi8, 0 },
131 { X86::OR32ri8, X86::OR32mi8 }, 156 { X86::OR64rr, X86::OR64mr, 0 },
132 { X86::OR32rr, X86::OR32mr }, 157 { X86::OR8ri, X86::OR8mi, 0 },
133 { X86::OR64ri32, X86::OR64mi32 }, 158 { X86::OR8rr, X86::OR8mr, 0 },
134 { X86::OR64ri8, X86::OR64mi8 }, 159 { X86::ROL16r1, X86::ROL16m1, 0 },
135 { X86::OR64rr, X86::OR64mr }, 160 { X86::ROL16rCL, X86::ROL16mCL, 0 },
136 { X86::OR8ri, X86::OR8mi }, 161 { X86::ROL16ri, X86::ROL16mi, 0 },
137 { X86::OR8rr, X86::OR8mr }, 162 { X86::ROL32r1, X86::ROL32m1, 0 },
138 { X86::ROL16r1, X86::ROL16m1 }, 163 { X86::ROL32rCL, X86::ROL32mCL, 0 },
139 { X86::ROL16rCL, X86::ROL16mCL }, 164 { X86::ROL32ri, X86::ROL32mi, 0 },
140 { X86::ROL16ri, X86::ROL16mi }, 165 { X86::ROL64r1, X86::ROL64m1, 0 },
141 { X86::ROL32r1, X86::ROL32m1 }, 166 { X86::ROL64rCL, X86::ROL64mCL, 0 },
142 { X86::ROL32rCL, X86::ROL32mCL }, 167 { X86::ROL64ri, X86::ROL64mi, 0 },
143 { X86::ROL32ri, X86::ROL32mi }, 168 { X86::ROL8r1, X86::ROL8m1, 0 },
144 { X86::ROL64r1, X86::ROL64m1 }, 169 { X86::ROL8rCL, X86::ROL8mCL, 0 },
145 { X86::ROL64rCL, X86::ROL64mCL }, 170 { X86::ROL8ri, X86::ROL8mi, 0 },
146 { X86::ROL64ri, X86::ROL64mi }, 171 { X86::ROR16r1, X86::ROR16m1, 0 },
147 { X86::ROL8r1, X86::ROL8m1 }, 172 { X86::ROR16rCL, X86::ROR16mCL, 0 },
148 { X86::ROL8rCL, X86::ROL8mCL }, 173 { X86::ROR16ri, X86::ROR16mi, 0 },
149 { X86::ROL8ri, X86::ROL8mi }, 174 { X86::ROR32r1, X86::ROR32m1, 0 },
150 { X86::ROR16r1, X86::ROR16m1 }, 175 { X86::ROR32rCL, X86::ROR32mCL, 0 },
151 { X86::ROR16rCL, X86::ROR16mCL }, 176 { X86::ROR32ri, X86::ROR32mi, 0 },
152 { X86::ROR16ri, X86::ROR16mi }, 177 { X86::ROR64r1, X86::ROR64m1, 0 },
153 { X86::ROR32r1, X86::ROR32m1 }, 178 { X86::ROR64rCL, X86::ROR64mCL, 0 },
154 { X86::ROR32rCL, X86::ROR32mCL }, 179 { X86::ROR64ri, X86::ROR64mi, 0 },
155 { X86::ROR32ri, X86::ROR32mi }, 180 { X86::ROR8r1, X86::ROR8m1, 0 },
156 { X86::ROR64r1, X86::ROR64m1 }, 181 { X86::ROR8rCL, X86::ROR8mCL, 0 },
157 { X86::ROR64rCL, X86::ROR64mCL }, 182 { X86::ROR8ri, X86::ROR8mi, 0 },
158 { X86::ROR64ri, X86::ROR64mi }, 183 { X86::SAR16r1, X86::SAR16m1, 0 },
159 { X86::ROR8r1, X86::ROR8m1 }, 184 { X86::SAR16rCL, X86::SAR16mCL, 0 },
160 { X86::ROR8rCL, X86::ROR8mCL }, 185 { X86::SAR16ri, X86::SAR16mi, 0 },
161 { X86::ROR8ri, X86::ROR8mi }, 186 { X86::SAR32r1, X86::SAR32m1, 0 },
162 { X86::SAR16r1, X86::SAR16m1 }, 187 { X86::SAR32rCL, X86::SAR32mCL, 0 },
163 { X86::SAR16rCL, X86::SAR16mCL }, 188 { X86::SAR32ri, X86::SAR32mi, 0 },
164 { X86::SAR16ri, X86::SAR16mi }, 189 { X86::SAR64r1, X86::SAR64m1, 0 },
165 { X86::SAR32r1, X86::SAR32m1 }, 190 { X86::SAR64rCL, X86::SAR64mCL, 0 },
166 { X86::SAR32rCL, X86::SAR32mCL }, 191 { X86::SAR64ri, X86::SAR64mi, 0 },
167 { X86::SAR32ri, X86::SAR32mi }, 192 { X86::SAR8r1, X86::SAR8m1, 0 },
168 { X86::SAR64r1, X86::SAR64m1 }, 193 { X86::SAR8rCL, X86::SAR8mCL, 0 },
169 { X86::SAR64rCL, X86::SAR64mCL }, 194 { X86::SAR8ri, X86::SAR8mi, 0 },
170 { X86::SAR64ri, X86::SAR64mi }, 195 { X86::SBB32ri, X86::SBB32mi, 0 },
171 { X86::SAR8r1, X86::SAR8m1 }, 196 { X86::SBB32ri8, X86::SBB32mi8, 0 },
172 { X86::SAR8rCL, X86::SAR8mCL }, 197 { X86::SBB32rr, X86::SBB32mr, 0 },
173 { X86::SAR8ri, X86::SAR8mi }, 198 { X86::SBB64ri32, X86::SBB64mi32, 0 },
174 { X86::SBB32ri, X86::SBB32mi }, 199 { X86::SBB64ri8, X86::SBB64mi8, 0 },
175 { X86::SBB32ri8, X86::SBB32mi8 }, 200 { X86::SBB64rr, X86::SBB64mr, 0 },
176 { X86::SBB32rr, X86::SBB32mr }, 201 { X86::SHL16rCL, X86::SHL16mCL, 0 },
177 { X86::SBB64ri32, X86::SBB64mi32 }, 202 { X86::SHL16ri, X86::SHL16mi, 0 },
178 { X86::SBB64ri8, X86::SBB64mi8 }, 203 { X86::SHL32rCL, X86::SHL32mCL, 0 },
179 { X86::SBB64rr, X86::SBB64mr }, 204 { X86::SHL32ri, X86::SHL32mi, 0 },
180 { X86::SHL16rCL, X86::SHL16mCL }, 205 { X86::SHL64rCL, X86::SHL64mCL, 0 },
181 { X86::SHL16ri, X86::SHL16mi }, 206 { X86::SHL64ri, X86::SHL64mi, 0 },
182 { X86::SHL32rCL, X86::SHL32mCL }, 207 { X86::SHL8rCL, X86::SHL8mCL, 0 },
183 { X86::SHL32ri, X86::SHL32mi }, 208 { X86::SHL8ri, X86::SHL8mi, 0 },
184 { X86::SHL64rCL, X86::SHL64mCL }, 209 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
185 { X86::SHL64ri, X86::SHL64mi }, 210 { X86::SHLD16rri8, X86::SHLD16mri8, 0 },
186 { X86::SHL8rCL, X86::SHL8mCL }, 211 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
187 { X86::SHL8ri, X86::SHL8mi }, 212 { X86::SHLD32rri8, X86::SHLD32mri8, 0 },
188 { X86::SHLD16rrCL, X86::SHLD16mrCL }, 213 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
189 { X86::SHLD16rri8, X86::SHLD16mri8 }, 214 { X86::SHLD64rri8, X86::SHLD64mri8, 0 },
190 { X86::SHLD32rrCL, X86::SHLD32mrCL }, 215 { X86::SHR16r1, X86::SHR16m1, 0 },
191 { X86::SHLD32rri8, X86::SHLD32mri8 }, 216 { X86::SHR16rCL, X86::SHR16mCL, 0 },
192 { X86::SHLD64rrCL, X86::SHLD64mrCL }, 217 { X86::SHR16ri, X86::SHR16mi, 0 },
193 { X86::SHLD64rri8, X86::SHLD64mri8 }, 218 { X86::SHR32r1, X86::SHR32m1, 0 },
194 { X86::SHR16r1, X86::SHR16m1 }, 219 { X86::SHR32rCL, X86::SHR32mCL, 0 },
195 { X86::SHR16rCL, X86::SHR16mCL }, 220 { X86::SHR32ri, X86::SHR32mi, 0 },
196 { X86::SHR16ri, X86::SHR16mi }, 221 { X86::SHR64r1, X86::SHR64m1, 0 },
197 { X86::SHR32r1, X86::SHR32m1 }, 222 { X86::SHR64rCL, X86::SHR64mCL, 0 },
198 { X86::SHR32rCL, X86::SHR32mCL }, 223 { X86::SHR64ri, X86::SHR64mi, 0 },
199 { X86::SHR32ri, X86::SHR32mi }, 224 { X86::SHR8r1, X86::SHR8m1, 0 },
200 { X86::SHR64r1, X86::SHR64m1 }, 225 { X86::SHR8rCL, X86::SHR8mCL, 0 },
201 { X86::SHR64rCL, X86::SHR64mCL }, 226 { X86::SHR8ri, X86::SHR8mi, 0 },
202 { X86::SHR64ri, X86::SHR64mi }, 227 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
203 { X86::SHR8r1, X86::SHR8m1 }, 228 { X86::SHRD16rri8, X86::SHRD16mri8, 0 },
204 { X86::SHR8rCL, X86::SHR8mCL }, 229 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
205 { X86::SHR8ri, X86::SHR8mi }, 230 { X86::SHRD32rri8, X86::SHRD32mri8, 0 },
206 { X86::SHRD16rrCL, X86::SHRD16mrCL }, 231 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
207 { X86::SHRD16rri8, X86::SHRD16mri8 }, 232 { X86::SHRD64rri8, X86::SHRD64mri8, 0 },
208 { X86::SHRD32rrCL, X86::SHRD32mrCL }, 233 { X86::SUB16ri, X86::SUB16mi, 0 },
209 { X86::SHRD32rri8, X86::SHRD32mri8 }, 234 { X86::SUB16ri8, X86::SUB16mi8, 0 },
210 { X86::SHRD64rrCL, X86::SHRD64mrCL }, 235 { X86::SUB16rr, X86::SUB16mr, 0 },
211 { X86::SHRD64rri8, X86::SHRD64mri8 }, 236 { X86::SUB32ri, X86::SUB32mi, 0 },
212 { X86::SUB16ri, X86::SUB16mi }, 237 { X86::SUB32ri8, X86::SUB32mi8, 0 },
213 { X86::SUB16ri8, X86::SUB16mi8 }, 238 { X86::SUB32rr, X86::SUB32mr, 0 },
214 { X86::SUB16rr, X86::SUB16mr }, 239 { X86::SUB64ri32, X86::SUB64mi32, 0 },
215 { X86::SUB32ri, X86::SUB32mi }, 240 { X86::SUB64ri8, X86::SUB64mi8, 0 },
216 { X86::SUB32ri8, X86::SUB32mi8 }, 241 { X86::SUB64rr, X86::SUB64mr, 0 },
217 { X86::SUB32rr, X86::SUB32mr }, 242 { X86::SUB8ri, X86::SUB8mi, 0 },
218 { X86::SUB64ri32, X86::SUB64mi32 }, 243 { X86::SUB8rr, X86::SUB8mr, 0 },
219 { X86::SUB64ri8, X86::SUB64mi8 }, 244 { X86::XOR16ri, X86::XOR16mi, 0 },
220 { X86::SUB64rr, X86::SUB64mr }, 245 { X86::XOR16ri8, X86::XOR16mi8, 0 },
221 { X86::SUB8ri, X86::SUB8mi }, 246 { X86::XOR16rr, X86::XOR16mr, 0 },
222 { X86::SUB8rr, X86::SUB8mr }, 247 { X86::XOR32ri, X86::XOR32mi, 0 },
223 { X86::XOR16ri, X86::XOR16mi }, 248 { X86::XOR32ri8, X86::XOR32mi8, 0 },
224 { X86::XOR16ri8, X86::XOR16mi8 }, 249 { X86::XOR32rr, X86::XOR32mr, 0 },
225 { X86::XOR16rr, X86::XOR16mr }, 250 { X86::XOR64ri32, X86::XOR64mi32, 0 },
226 { X86::XOR32ri, X86::XOR32mi }, 251 { X86::XOR64ri8, X86::XOR64mi8, 0 },
227 { X86::XOR32ri8, X86::XOR32mi8 }, 252 { X86::XOR64rr, X86::XOR64mr, 0 },
228 { X86::XOR32rr, X86::XOR32mr }, 253 { X86::XOR8ri, X86::XOR8mi, 0 },
229 { X86::XOR64ri32, X86::XOR64mi32 }, 254 { X86::XOR8rr, X86::XOR8mr, 0 }
230 { X86::XOR64ri8, X86::XOR64mi8 },
231 { X86::XOR64rr, X86::XOR64mr },
232 { X86::XOR8ri, X86::XOR8mi },
233 { X86::XOR8rr, X86::XOR8mr }
234 }; 255 };
235 256
236 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) { 257 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
237 unsigned RegOp = OpTbl2Addr[i][0]; 258 unsigned RegOp = OpTbl2Addr[i][0];
238 unsigned MemOp = OpTbl2Addr[i][1] & ~TB_FLAGS; 259 unsigned MemOp = OpTbl2Addr[i][1];
239 assert(!RegOp2MemOpTable2Addr.count(RegOp) && "Duplicated entries?"); 260 unsigned Flags = OpTbl2Addr[i][2];
240 RegOp2MemOpTable2Addr[RegOp] = std::make_pair(MemOp, 0U); 261 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
241 262 RegOp, MemOp,
242 // If this is not a reversible operation (because there is a many->one) 263 // Index 0, folded load and store, no alignment requirement.
243 // mapping, don't insert the reverse of the operation into MemOp2RegOpTable. 264 Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
244 if (OpTbl2Addr[i][1] & TB_NOT_REVERSABLE)
245 continue;
246
247 // Index 0, folded load and store, no alignment requirement.
248 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5);
249
250 assert(!MemOp2RegOpTable.count(MemOp) &&
251 "Duplicated entries in unfolding maps?");
252 MemOp2RegOpTable[MemOp] = std::make_pair(RegOp, AuxInfo);
253 } 265 }
254 266
255 // If the third value is 1, then it's folding either a load or a store. 267 static const unsigned OpTbl0[][3] = {
256 static const unsigned OpTbl0[][4] = { 268 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD },
257 { X86::BT16ri8, X86::BT16mi8, 1, 0 }, 269 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD },
258 { X86::BT32ri8, X86::BT32mi8, 1, 0 }, 270 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD },
259 { X86::BT64ri8, X86::BT64mi8, 1, 0 }, 271 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD },
260 { X86::CALL32r, X86::CALL32m, 1, 0 }, 272 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD },
261 { X86::CALL64r, X86::CALL64m, 1, 0 }, 273 { X86::WINCALL64r, X86::WINCALL64m, TB_FOLDED_LOAD },
262 { X86::WINCALL64r, X86::WINCALL64m, 1, 0 }, 274 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD },
263 { X86::CMP16ri, X86::CMP16mi, 1, 0 }, 275 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD },
264 { X86::CMP16ri8, X86::CMP16mi8, 1, 0 }, 276 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD },
265 { X86::CMP16rr, X86::CMP16mr, 1, 0 }, 277 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD },
266 { X86::CMP32ri, X86::CMP32mi, 1, 0 }, 278 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD },
267 { X86::CMP32ri8, X86::CMP32mi8, 1, 0 }, 279 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD },
268 { X86::CMP32rr, X86::CMP32mr, 1, 0 }, 280 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD },
269 { X86::CMP64ri32, X86::CMP64mi32, 1, 0 }, 281 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD },
270 { X86::CMP64ri8, X86::CMP64mi8, 1, 0 }, 282 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD },
271 { X86::CMP64rr, X86::CMP64mr, 1, 0 }, 283 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD },
272 { X86::CMP8ri, X86::CMP8mi, 1, 0 }, 284 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD },
273 { X86::CMP8rr, X86::CMP8mr, 1, 0 }, 285 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD },
274 { X86::DIV16r, X86::DIV16m, 1, 0 }, 286 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD },
275 { X86::DIV32r, X86::DIV32m, 1, 0 }, 287 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD },
276 { X86::DIV64r, X86::DIV64m, 1, 0 }, 288 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD },
277 { X86::DIV8r, X86::DIV8m, 1, 0 }, 289 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
278 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0, 16 }, 290 { X86::FsMOVAPDrr, X86::MOVSDmr, TB_FOLDED_STORE | TB_NO_REVERSE },
279 { X86::FsMOVAPDrr, X86::MOVSDmr | TB_NOT_REVERSABLE , 0, 0 }, 291 { X86::FsMOVAPSrr, X86::MOVSSmr, TB_FOLDED_STORE | TB_NO_REVERSE },
280 { X86::FsMOVAPSrr, X86::MOVSSmr | TB_NOT_REVERSABLE , 0, 0 }, 292 { X86::FsVMOVAPDrr, X86::VMOVSDmr, TB_FOLDED_STORE | TB_NO_REVERSE },
281 { X86::FsVMOVAPDrr, X86::VMOVSDmr | TB_NOT_REVERSABLE , 0, 0 }, 293 { X86::FsVMOVAPSrr, X86::VMOVSSmr, TB_FOLDED_STORE | TB_NO_REVERSE },
282 { X86::FsVMOVAPSrr, X86::VMOVSSmr | TB_NOT_REVERSABLE , 0, 0 }, 294 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD },
283 { X86::IDIV16r, X86::IDIV16m, 1, 0 }, 295 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD },
284 { X86::IDIV32r, X86::IDIV32m, 1, 0 }, 296 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD },
285 { X86::IDIV64r, X86::IDIV64m, 1, 0 }, 297 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD },
286 { X86::IDIV8r, X86::IDIV8m, 1, 0 }, 298 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD },
287 { X86::IMUL16r, X86::IMUL16m, 1, 0 }, 299 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD },
288 { X86::IMUL32r, X86::IMUL32m, 1, 0 }, 300 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD },
289 { X86::IMUL64r, X86::IMUL64m, 1, 0 }, 301 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD },
290 { X86::IMUL8r, X86::IMUL8m, 1, 0 }, 302 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD },
291 { X86::JMP32r, X86::JMP32m, 1, 0 }, 303 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD },
292 { X86::JMP64r, X86::JMP64m, 1, 0 }, 304 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE },
293 { X86::MOV16ri, X86::MOV16mi, 0, 0 }, 305 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE },
294 { X86::MOV16rr, X86::MOV16mr, 0, 0 }, 306 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE },
295 { X86::MOV32ri, X86::MOV32mi, 0, 0 }, 307 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE },
296 { X86::MOV32rr, X86::MOV32mr, 0, 0 }, 308 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE },
297 { X86::MOV64ri32, X86::MOV64mi32, 0, 0 }, 309 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE },
298 { X86::MOV64rr, X86::MOV64mr, 0, 0 }, 310 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE },
299 { X86::MOV8ri, X86::MOV8mi, 0, 0 }, 311 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE },
300 { X86::MOV8rr, X86::MOV8mr, 0, 0 }, 312 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
301 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, 0, 0 }, 313 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
302 { X86::MOVAPDrr, X86::MOVAPDmr, 0, 16 }, 314 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
303 { X86::MOVAPSrr, X86::MOVAPSmr, 0, 16 }, 315 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
304 { X86::MOVDQArr, X86::MOVDQAmr, 0, 16 }, 316 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
305 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, 0, 32 }, 317 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
306 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, 0, 32 }, 318 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
307 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, 0, 32 }, 319 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE },
308 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0, 0 }, 320 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE },
309 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0, 0 }, 321 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE },
310 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0, 0 }, 322 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE },
311 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0, 0 }, 323 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE },
312 { X86::MOVUPDrr, X86::MOVUPDmr, 0, 0 }, 324 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE },
313 { X86::MOVUPSrr, X86::MOVUPSmr, 0, 0 }, 325 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE },
314 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, 0, 0 }, 326 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE },
315 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, 0, 0 }, 327 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD },
316 { X86::MUL16r, X86::MUL16m, 1, 0 }, 328 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD },
317 { X86::MUL32r, X86::MUL32m, 1, 0 }, 329 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD },
318 { X86::MUL64r, X86::MUL64m, 1, 0 }, 330 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD },
319 { X86::MUL8r, X86::MUL8m, 1, 0 }, 331 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE },
320 { X86::SETAEr, X86::SETAEm, 0, 0 }, 332 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE },
321 { X86::SETAr, X86::SETAm, 0, 0 }, 333 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE },
322 { X86::SETBEr, X86::SETBEm, 0, 0 }, 334 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE },
323 { X86::SETBr, X86::SETBm, 0, 0 }, 335 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE },
324 { X86::SETEr, X86::SETEm, 0, 0 }, 336 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE },
325 { X86::SETGEr, X86::SETGEm, 0, 0 }, 337 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE },
326 { X86::SETGr, X86::SETGm, 0, 0 }, 338 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE },
327 { X86::SETLEr, X86::SETLEm, 0, 0 }, 339 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE },
328 { X86::SETLr, X86::SETLm, 0, 0 }, 340 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE },
329 { X86::SETNEr, X86::SETNEm, 0, 0 }, 341 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE },
330 { X86::SETNOr, X86::SETNOm, 0, 0 }, 342 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE },
331 { X86::SETNPr, X86::SETNPm, 0, 0 }, 343 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE },
332 { X86::SETNSr, X86::SETNSm, 0, 0 }, 344 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE },
333 { X86::SETOr, X86::SETOm, 0, 0 }, 345 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE },
334 { X86::SETPr, X86::SETPm, 0, 0 }, 346 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE },
335 { X86::SETSr, X86::SETSm, 0, 0 }, 347 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD },
336 { X86::TAILJMPr, X86::TAILJMPm, 1, 0 }, 348 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD },
337 { X86::TAILJMPr64, X86::TAILJMPm64, 1, 0 }, 349 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD },
338 { X86::TEST16ri, X86::TEST16mi, 1, 0 }, 350 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD },
339 { X86::TEST32ri, X86::TEST32mi, 1, 0 }, 351 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD },
340 { X86::TEST64ri32, X86::TEST64mi32, 1, 0 }, 352 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD }
341 { X86::TEST8ri, X86::TEST8mi, 1, 0 }
342 }; 353 };
343 354
344 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) { 355 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
345 unsigned RegOp = OpTbl0[i][0]; 356 unsigned RegOp = OpTbl0[i][0];
346 unsigned MemOp = OpTbl0[i][1] & ~TB_FLAGS; 357 unsigned MemOp = OpTbl0[i][1];
347 unsigned FoldedLoad = OpTbl0[i][2]; 358 unsigned Flags = OpTbl0[i][2];
348 unsigned Align = OpTbl0[i][3]; 359 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
349 assert(!RegOp2MemOpTable0.count(RegOp) && "Duplicated entries?"); 360 RegOp, MemOp, TB_INDEX_0 | Flags);
350 RegOp2MemOpTable0[RegOp] = std::make_pair(MemOp, Align);
351
352 // If this is not a reversible operation (because there is a many->one)
353 // mapping, don't insert the reverse of the operation into MemOp2RegOpTable.
354 if (OpTbl0[i][1] & TB_NOT_REVERSABLE)
355 continue;
356
357 // Index 0, folded load or store.
358 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
359 assert(!MemOp2RegOpTable.count(MemOp) && "Duplicated entries?");
360 MemOp2RegOpTable[MemOp] = std::make_pair(RegOp, AuxInfo);
361 } 361 }
362 362
363 static const unsigned OpTbl1[][3] = { 363 static const unsigned OpTbl1[][3] = {
364 { X86::CMP16rr, X86::CMP16rm, 0 }, 364 { X86::CMP16rr, X86::CMP16rm, 0 },
365 { X86::CMP32rr, X86::CMP32rm, 0 }, 365 { X86::CMP32rr, X86::CMP32rm, 0 },
366 { X86::CMP64rr, X86::CMP64rm, 0 }, 366 { X86::CMP64rr, X86::CMP64rm, 0 },
367 { X86::CMP8rr, X86::CMP8rm, 0 }, 367 { X86::CMP8rr, X86::CMP8rm, 0 },
368 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 }, 368 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
369 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 }, 369 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
370 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 }, 370 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
371 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 }, 371 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
372 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 }, 372 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
373 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 }, 373 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
374 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 }, 374 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
375 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 }, 375 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
376 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 }, 376 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
377 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 }, 377 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
378 { X86::FsMOVAPDrr, X86::MOVSDrm | TB_NOT_REVERSABLE , 0 }, 378 { X86::FsMOVAPDrr, X86::MOVSDrm, TB_NO_REVERSE },
379 { X86::FsMOVAPSrr, X86::MOVSSrm | TB_NOT_REVERSABLE , 0 }, 379 { X86::FsMOVAPSrr, X86::MOVSSrm, TB_NO_REVERSE },
380 { X86::FsVMOVAPDrr, X86::VMOVSDrm | TB_NOT_REVERSABLE , 0 }, 380 { X86::FsVMOVAPDrr, X86::VMOVSDrm, TB_NO_REVERSE },
381 { X86::FsVMOVAPSrr, X86::VMOVSSrm | TB_NOT_REVERSABLE , 0 }, 381 { X86::FsVMOVAPSrr, X86::VMOVSSrm, TB_NO_REVERSE },
382 { X86::IMUL16rri, X86::IMUL16rmi, 0 }, 382 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
383 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 }, 383 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
384 { X86::IMUL32rri, X86::IMUL32rmi, 0 }, 384 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
385 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 }, 385 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
386 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 }, 386 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
387 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 }, 387 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
388 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 }, 388 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
389 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 }, 389 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
390 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm, 16 }, 390 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm, TB_ALIGN_16 },
391 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm, 16 }, 391 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm, TB_ALIGN_16 },
392 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm, 16 }, 392 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm, TB_ALIGN_16 },
393 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm, 16 }, 393 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm, TB_ALIGN_16 },
394 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm, 16 }, 394 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm, TB_ALIGN_16 },
395 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, 0 }, 395 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, 0 },
396 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 }, 396 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
397 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 }, 397 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
398 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 }, 398 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
399 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 }, 399 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
400 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 }, 400 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
401 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 }, 401 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
402 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 }, 402 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
403 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 }, 403 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
404 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, 16 }, 404 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 },
405 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, 16 }, 405 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 },
406 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 }, 406 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
407 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 }, 407 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
408 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 }, 408 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
409 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 }, 409 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
410 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 }, 410 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
411 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 }, 411 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
412 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 }, 412 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 },
413 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 }, 413 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 },
414 { X86::MOV16rr, X86::MOV16rm, 0 }, 414 { X86::MOV16rr, X86::MOV16rm, 0 },
415 { X86::MOV32rr, X86::MOV32rm, 0 }, 415 { X86::MOV32rr, X86::MOV32rm, 0 },
416 { X86::MOV64rr, X86::MOV64rm, 0 }, 416 { X86::MOV64rr, X86::MOV64rm, 0 },
417 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 }, 417 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
418 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 }, 418 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
419 { X86::MOV8rr, X86::MOV8rm, 0 }, 419 { X86::MOV8rr, X86::MOV8rm, 0 },
420 { X86::MOVAPDrr, X86::MOVAPDrm, 16 }, 420 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 },
421 { X86::MOVAPSrr, X86::MOVAPSrm, 16 }, 421 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 },
422 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, 32 }, 422 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 },
423 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, 32 }, 423 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 },
424 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 }, 424 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
425 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 }, 425 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
426 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 }, 426 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
427 { X86::MOVDQArr, X86::MOVDQArm, 16 }, 427 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 },
428 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, 16 }, 428 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_16 },
429 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, 16 }, 429 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 },
430 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, 16 }, 430 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 },
431 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 }, 431 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
432 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 }, 432 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
433 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 }, 433 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
434 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 }, 434 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
435 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 }, 435 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
436 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 }, 436 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
437 { X86::MOVUPDrr, X86::MOVUPDrm, 16 }, 437 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 },
438 { X86::MOVUPSrr, X86::MOVUPSrm, 0 }, 438 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
439 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 }, 439 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
440 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 }, 440 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 },
441 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 }, 441 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 },
442 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 }, 442 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
443 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, 16 }, 443 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 },
444 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 }, 444 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
445 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 }, 445 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
446 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 }, 446 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
447 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 }, 447 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
448 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 }, 448 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 },
449 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 }, 449 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 },
450 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 }, 450 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 },
451 { X86::PSHUFDri, X86::PSHUFDmi, 16 }, 451 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 },
452 { X86::PSHUFHWri, X86::PSHUFHWmi, 16 }, 452 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 },
453 { X86::PSHUFLWri, X86::PSHUFLWmi, 16 }, 453 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 },
454 { X86::RCPPSr, X86::RCPPSm, 16 }, 454 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 },
455 { X86::RCPPSr_Int, X86::RCPPSm_Int, 16 }, 455 { X86::RCPPSr_Int, X86::RCPPSm_Int, TB_ALIGN_16 },
456 { X86::RSQRTPSr, X86::RSQRTPSm, 16 }, 456 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 },
457 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, 16 }, 457 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, TB_ALIGN_16 },
458 { X86::RSQRTSSr, X86::RSQRTSSm, 0 }, 458 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
459 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 }, 459 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
460 { X86::SQRTPDr, X86::SQRTPDm, 16 }, 460 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 },
461 { X86::SQRTPDr_Int, X86::SQRTPDm_Int, 16 }, 461 { X86::SQRTPDr_Int, X86::SQRTPDm_Int, TB_ALIGN_16 },
462 { X86::SQRTPSr, X86::SQRTPSm, 16 }, 462 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 },
463 { X86::SQRTPSr_Int, X86::SQRTPSm_Int, 16 }, 463 { X86::SQRTPSr_Int, X86::SQRTPSm_Int, TB_ALIGN_16 },
464 { X86::SQRTSDr, X86::SQRTSDm, 0 }, 464 { X86::SQRTSDr, X86::SQRTSDm, 0 },
465 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 }, 465 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
466 { X86::SQRTSSr, X86::SQRTSSm, 0 }, 466 { X86::SQRTSSr, X86::SQRTSSm, 0 },
467 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 }, 467 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
468 { X86::TEST16rr, X86::TEST16rm, 0 }, 468 { X86::TEST16rr, X86::TEST16rm, 0 },
469 { X86::TEST32rr, X86::TEST32rm, 0 }, 469 { X86::TEST32rr, X86::TEST32rm, 0 },
470 { X86::TEST64rr, X86::TEST64rm, 0 }, 470 { X86::TEST64rr, X86::TEST64rm, 0 },
471 { X86::TEST8rr, X86::TEST8rm, 0 }, 471 { X86::TEST8rr, X86::TEST8rm, 0 },
472 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0 472 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
473 { X86::UCOMISDrr, X86::UCOMISDrm, 0 }, 473 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
474 { X86::UCOMISSrr, X86::UCOMISSrm, 0 }, 474 { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
475 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 }, 475 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
476 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 } 476 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 }
477 }; 477 };
478 478
479 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) { 479 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
480 unsigned RegOp = OpTbl1[i][0]; 480 unsigned RegOp = OpTbl1[i][0];
481 unsigned MemOp = OpTbl1[i][1] & ~TB_FLAGS; 481 unsigned MemOp = OpTbl1[i][1];
482 unsigned Align = OpTbl1[i][2]; 482 unsigned Flags = OpTbl1[i][2];
483 assert(!RegOp2MemOpTable1.count(RegOp) && "Duplicate entries"); 483 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
484 RegOp2MemOpTable1[RegOp] = std::make_pair(MemOp, Align); 484 RegOp, MemOp,
485 485 // Index 1, folded load
486 // If this is not a reversible operation (because there is a many->one) 486 Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
487 // mapping, don't insert the reverse of the operation into MemOp2RegOpTable.
488 if (OpTbl1[i][1] & TB_NOT_REVERSABLE)
489 continue;
490
491 // Index 1, folded load
492 unsigned AuxInfo = 1 | (1 << 4);
493 assert(!MemOp2RegOpTable.count(MemOp) && "Duplicate entries");
494 MemOp2RegOpTable[MemOp] = std::make_pair(RegOp, AuxInfo);
495 } 487 }
496 488
497 static const unsigned OpTbl2[][3] = { 489 static const unsigned OpTbl2[][3] = {
498 { X86::ADC32rr, X86::ADC32rm, 0 }, 490 { X86::ADC32rr, X86::ADC32rm, 0 },
499 { X86::ADC64rr, X86::ADC64rm, 0 }, 491 { X86::ADC64rr, X86::ADC64rm, 0 },
500 { X86::ADD16rr, X86::ADD16rm, 0 }, 492 { X86::ADD16rr, X86::ADD16rm, 0 },
501 { X86::ADD16rr_DB, X86::ADD16rm | TB_NOT_REVERSABLE, 0 }, 493 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE },
502 { X86::ADD32rr, X86::ADD32rm, 0 }, 494 { X86::ADD32rr, X86::ADD32rm, 0 },
503 { X86::ADD32rr_DB, X86::ADD32rm | TB_NOT_REVERSABLE, 0 }, 495 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE },
504 { X86::ADD64rr, X86::ADD64rm, 0 }, 496 { X86::ADD64rr, X86::ADD64rm, 0 },
505 { X86::ADD64rr_DB, X86::ADD64rm | TB_NOT_REVERSABLE, 0 }, 497 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE },
506 { X86::ADD8rr, X86::ADD8rm, 0 }, 498 { X86::ADD8rr, X86::ADD8rm, 0 },
507 { X86::ADDPDrr, X86::ADDPDrm, 16 }, 499 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 },
508 { X86::ADDPSrr, X86::ADDPSrm, 16 }, 500 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 },
509 { X86::ADDSDrr, X86::ADDSDrm, 0 }, 501 { X86::ADDSDrr, X86::ADDSDrm, 0 },
510 { X86::ADDSSrr, X86::ADDSSrm, 0 }, 502 { X86::ADDSSrr, X86::ADDSSrm, 0 },
511 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, 16 }, 503 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 },
512 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, 16 }, 504 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 },
513 { X86::AND16rr, X86::AND16rm, 0 }, 505 { X86::AND16rr, X86::AND16rm, 0 },
514 { X86::AND32rr, X86::AND32rm, 0 }, 506 { X86::AND32rr, X86::AND32rm, 0 },
515 { X86::AND64rr, X86::AND64rm, 0 }, 507 { X86::AND64rr, X86::AND64rm, 0 },
516 { X86::AND8rr, X86::AND8rm, 0 }, 508 { X86::AND8rr, X86::AND8rm, 0 },
517 { X86::ANDNPDrr, X86::ANDNPDrm, 16 }, 509 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 },
518 { X86::ANDNPSrr, X86::ANDNPSrm, 16 }, 510 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 },
519 { X86::ANDPDrr, X86::ANDPDrm, 16 }, 511 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 },
520 { X86::ANDPSrr, X86::ANDPSrm, 16 }, 512 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 },
521 { X86::CMOVA16rr, X86::CMOVA16rm, 0 }, 513 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
522 { X86::CMOVA32rr, X86::CMOVA32rm, 0 }, 514 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
523 { X86::CMOVA64rr, X86::CMOVA64rm, 0 }, 515 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
524 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 }, 516 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
525 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 }, 517 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
526 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 }, 518 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
527 { X86::CMOVB16rr, X86::CMOVB16rm, 0 }, 519 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
528 { X86::CMOVB32rr, X86::CMOVB32rm, 0 }, 520 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
529 { X86::CMOVB64rr, X86::CMOVB64rm, 0 }, 521 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
530 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 }, 522 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
531 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 }, 523 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
532 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 }, 524 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
533 { X86::CMOVE16rr, X86::CMOVE16rm, 0 }, 525 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
534 { X86::CMOVE32rr, X86::CMOVE32rm, 0 }, 526 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
535 { X86::CMOVE64rr, X86::CMOVE64rm, 0 }, 527 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
536 { X86::CMOVG16rr, X86::CMOVG16rm, 0 }, 528 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
537 { X86::CMOVG32rr, X86::CMOVG32rm, 0 }, 529 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
538 { X86::CMOVG64rr, X86::CMOVG64rm, 0 }, 530 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
539 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 }, 531 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
540 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 }, 532 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
541 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 }, 533 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
542 { X86::CMOVL16rr, X86::CMOVL16rm, 0 }, 534 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
543 { X86::CMOVL32rr, X86::CMOVL32rm, 0 }, 535 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
544 { X86::CMOVL64rr, X86::CMOVL64rm, 0 }, 536 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
545 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 }, 537 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
546 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 }, 538 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
547 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 }, 539 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
548 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 }, 540 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
549 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 }, 541 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
550 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 }, 542 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
551 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 }, 543 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
552 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 }, 544 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
553 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 }, 545 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
554 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 }, 546 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
555 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 }, 547 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
556 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 }, 548 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
557 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 }, 549 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
558 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 }, 550 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
559 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 }, 551 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
560 { X86::CMOVO16rr, X86::CMOVO16rm, 0 }, 552 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
561 { X86::CMOVO32rr, X86::CMOVO32rm, 0 }, 553 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
562 { X86::CMOVO64rr, X86::CMOVO64rm, 0 }, 554 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
563 { X86::CMOVP16rr, X86::CMOVP16rm, 0 }, 555 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
564 { X86::CMOVP32rr, X86::CMOVP32rm, 0 }, 556 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
565 { X86::CMOVP64rr, X86::CMOVP64rm, 0 }, 557 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
566 { X86::CMOVS16rr, X86::CMOVS16rm, 0 }, 558 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
567 { X86::CMOVS32rr, X86::CMOVS32rm, 0 }, 559 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
568 { X86::CMOVS64rr, X86::CMOVS64rm, 0 }, 560 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
569 { X86::CMPPDrri, X86::CMPPDrmi, 16 }, 561 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 },
570 { X86::CMPPSrri, X86::CMPPSrmi, 16 }, 562 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 },
571 { X86::CMPSDrr, X86::CMPSDrm, 0 }, 563 { X86::CMPSDrr, X86::CMPSDrm, 0 },
572 { X86::CMPSSrr, X86::CMPSSrm, 0 }, 564 { X86::CMPSSrr, X86::CMPSSrm, 0 },
573 { X86::DIVPDrr, X86::DIVPDrm, 16 }, 565 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 },
574 { X86::DIVPSrr, X86::DIVPSrm, 16 }, 566 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 },
575 { X86::DIVSDrr, X86::DIVSDrm, 0 }, 567 { X86::DIVSDrr, X86::DIVSDrm, 0 },
576 { X86::DIVSSrr, X86::DIVSSrm, 0 }, 568 { X86::DIVSSrr, X86::DIVSSrm, 0 },
577 { X86::FsANDNPDrr, X86::FsANDNPDrm, 16 }, 569 { X86::FsANDNPDrr, X86::FsANDNPDrm, TB_ALIGN_16 },
578 { X86::FsANDNPSrr, X86::FsANDNPSrm, 16 }, 570 { X86::FsANDNPSrr, X86::FsANDNPSrm, TB_ALIGN_16 },
579 { X86::FsANDPDrr, X86::FsANDPDrm, 16 }, 571 { X86::FsANDPDrr, X86::FsANDPDrm, TB_ALIGN_16 },
580 { X86::FsANDPSrr, X86::FsANDPSrm, 16 }, 572 { X86::FsANDPSrr, X86::FsANDPSrm, TB_ALIGN_16 },
581 { X86::FsORPDrr, X86::FsORPDrm, 16 }, 573 { X86::FsORPDrr, X86::FsORPDrm, TB_ALIGN_16 },
582 { X86::FsORPSrr, X86::FsORPSrm, 16 }, 574 { X86::FsORPSrr, X86::FsORPSrm, TB_ALIGN_16 },
583 { X86::FsXORPDrr, X86::FsXORPDrm, 16 }, 575 { X86::FsXORPDrr, X86::FsXORPDrm, TB_ALIGN_16 },
584 { X86::FsXORPSrr, X86::FsXORPSrm, 16 }, 576 { X86::FsXORPSrr, X86::FsXORPSrm, TB_ALIGN_16 },
585 { X86::HADDPDrr, X86::HADDPDrm, 16 }, 577 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 },
586 { X86::HADDPSrr, X86::HADDPSrm, 16 }, 578 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 },
587 { X86::HSUBPDrr, X86::HSUBPDrm, 16 }, 579 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 },
588 { X86::HSUBPSrr, X86::HSUBPSrm, 16 }, 580 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 },
589 { X86::IMUL16rr, X86::IMUL16rm, 0 }, 581 { X86::IMUL16rr, X86::IMUL16rm, 0 },
590 { X86::IMUL32rr, X86::IMUL32rm, 0 }, 582 { X86::IMUL32rr, X86::IMUL32rm, 0 },
591 { X86::IMUL64rr, X86::IMUL64rm, 0 }, 583 { X86::IMUL64rr, X86::IMUL64rm, 0 },
592 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 }, 584 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
593 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 }, 585 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
594 { X86::MAXPDrr, X86::MAXPDrm, 16 }, 586 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 },
595 { X86::MAXPDrr_Int, X86::MAXPDrm_Int, 16 }, 587 { X86::MAXPDrr_Int, X86::MAXPDrm_Int, TB_ALIGN_16 },
596 { X86::MAXPSrr, X86::MAXPSrm, 16 }, 588 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 },
597 { X86::MAXPSrr_Int, X86::MAXPSrm_Int, 16 }, 589 { X86::MAXPSrr_Int, X86::MAXPSrm_Int, TB_ALIGN_16 },
598 { X86::MAXSDrr, X86::MAXSDrm, 0 }, 590 { X86::MAXSDrr, X86::MAXSDrm, 0 },
599 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 }, 591 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
600 { X86::MAXSSrr, X86::MAXSSrm, 0 }, 592 { X86::MAXSSrr, X86::MAXSSrm, 0 },
601 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 }, 593 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
602 { X86::MINPDrr, X86::MINPDrm, 16 }, 594 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 },
603 { X86::MINPDrr_Int, X86::MINPDrm_Int, 16 }, 595 { X86::MINPDrr_Int, X86::MINPDrm_Int, TB_ALIGN_16 },
604 { X86::MINPSrr, X86::MINPSrm, 16 }, 596 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 },
605 { X86::MINPSrr_Int, X86::MINPSrm_Int, 16 }, 597 { X86::MINPSrr_Int, X86::MINPSrm_Int, TB_ALIGN_16 },
606 { X86::MINSDrr, X86::MINSDrm, 0 }, 598 { X86::MINSDrr, X86::MINSDrm, 0 },
607 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 }, 599 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
608 { X86::MINSSrr, X86::MINSSrm, 0 }, 600 { X86::MINSSrr, X86::MINSSrm, 0 },
609 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 }, 601 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
610 { X86::MULPDrr, X86::MULPDrm, 16 }, 602 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 },
611 { X86::MULPSrr, X86::MULPSrm, 16 }, 603 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 },
612 { X86::MULSDrr, X86::MULSDrm, 0 }, 604 { X86::MULSDrr, X86::MULSDrm, 0 },
613 { X86::MULSSrr, X86::MULSSrm, 0 }, 605 { X86::MULSSrr, X86::MULSSrm, 0 },
614 { X86::OR16rr, X86::OR16rm, 0 }, 606 { X86::OR16rr, X86::OR16rm, 0 },
615 { X86::OR32rr, X86::OR32rm, 0 }, 607 { X86::OR32rr, X86::OR32rm, 0 },
616 { X86::OR64rr, X86::OR64rm, 0 }, 608 { X86::OR64rr, X86::OR64rm, 0 },
617 { X86::OR8rr, X86::OR8rm, 0 }, 609 { X86::OR8rr, X86::OR8rm, 0 },
618 { X86::ORPDrr, X86::ORPDrm, 16 }, 610 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 },
619 { X86::ORPSrr, X86::ORPSrm, 16 }, 611 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 },
620 { X86::PACKSSDWrr, X86::PACKSSDWrm, 16 }, 612 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 },
621 { X86::PACKSSWBrr, X86::PACKSSWBrm, 16 }, 613 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 },
622 { X86::PACKUSWBrr, X86::PACKUSWBrm, 16 }, 614 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 },
623 { X86::PADDBrr, X86::PADDBrm, 16 }, 615 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 },
624 { X86::PADDDrr, X86::PADDDrm, 16 }, 616 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 },
625 { X86::PADDQrr, X86::PADDQrm, 16 }, 617 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 },
626 { X86::PADDSBrr, X86::PADDSBrm, 16 }, 618 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 },
627 { X86::PADDSWrr, X86::PADDSWrm, 16 }, 619 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 },
628 { X86::PADDWrr, X86::PADDWrm, 16 }, 620 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 },
629 { X86::PANDNrr, X86::PANDNrm, 16 }, 621 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 },
630 { X86::PANDrr, X86::PANDrm, 16 }, 622 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 },
631 { X86::PAVGBrr, X86::PAVGBrm, 16 }, 623 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 },
632 { X86::PAVGWrr, X86::PAVGWrm, 16 }, 624 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 },
633 { X86::PCMPEQBrr, X86::PCMPEQBrm, 16 }, 625 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 },
634 { X86::PCMPEQDrr, X86::PCMPEQDrm, 16 }, 626 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 },
635 { X86::PCMPEQWrr, X86::PCMPEQWrm, 16 }, 627 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 },
636 { X86::PCMPGTBrr, X86::PCMPGTBrm, 16 }, 628 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 },
637 { X86::PCMPGTDrr, X86::PCMPGTDrm, 16 }, 629 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 },
638 { X86::PCMPGTWrr, X86::PCMPGTWrm, 16 }, 630 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 },
639 { X86::PINSRWrri, X86::PINSRWrmi, 16 }, 631 { X86::PINSRWrri, X86::PINSRWrmi, TB_ALIGN_16 },
640 { X86::PMADDWDrr, X86::PMADDWDrm, 16 }, 632 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
641 { X86::PMAXSWrr, X86::PMAXSWrm, 16 }, 633 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 },
642 { X86::PMAXUBrr, X86::PMAXUBrm, 16 }, 634 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 },
643 { X86::PMINSWrr, X86::PMINSWrm, 16 }, 635 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 },
644 { X86::PMINUBrr, X86::PMINUBrm, 16 }, 636 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 },
645 { X86::PMULDQrr, X86::PMULDQrm, 16 }, 637 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 },
646 { X86::PMULHUWrr, X86::PMULHUWrm, 16 }, 638 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 },
647 { X86::PMULHWrr, X86::PMULHWrm, 16 }, 639 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 },
648 { X86::PMULLDrr, X86::PMULLDrm, 16 }, 640 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 },
649 { X86::PMULLWrr, X86::PMULLWrm, 16 }, 641 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 },
650 { X86::PMULUDQrr, X86::PMULUDQrm, 16 }, 642 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 },
651 { X86::PORrr, X86::PORrm, 16 }, 643 { X86::PORrr, X86::PORrm, TB_ALIGN_16 },
652 { X86::PSADBWrr, X86::PSADBWrm, 16 }, 644 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
653 { X86::PSLLDrr, X86::PSLLDrm, 16 }, 645 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
654 { X86::PSLLQrr, X86::PSLLQrm, 16 }, 646 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
655 { X86::PSLLWrr, X86::PSLLWrm, 16 }, 647 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
656 { X86::PSRADrr, X86::PSRADrm, 16 }, 648 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 },
657 { X86::PSRAWrr, X86::PSRAWrm, 16 }, 649 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 },
658 { X86::PSRLDrr, X86::PSRLDrm, 16 }, 650 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 },
659 { X86::PSRLQrr, X86::PSRLQrm, 16 }, 651 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 },
660 { X86::PSRLWrr, X86::PSRLWrm, 16 }, 652 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 },
661 { X86::PSUBBrr, X86::PSUBBrm, 16 }, 653 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 },
662 { X86::PSUBDrr, X86::PSUBDrm, 16 }, 654 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 },
663 { X86::PSUBSBrr, X86::PSUBSBrm, 16 }, 655 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 },
664 { X86::PSUBSWrr, X86::PSUBSWrm, 16 }, 656 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 },
665 { X86::PSUBWrr, X86::PSUBWrm, 16 }, 657 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 },
666 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, 16 }, 658 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 },
667 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, 16 }, 659 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 },
668 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, 16 }, 660 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 },
669 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, 16 }, 661 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 },
670 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, 16 }, 662 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 },
671 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, 16 }, 663 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 },
672 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, 16 }, 664 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 },
673 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, 16 }, 665 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 },
674 { X86::PXORrr, X86::PXORrm, 16 }, 666 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 },
675 { X86::SBB32rr, X86::SBB32rm, 0 }, 667 { X86::SBB32rr, X86::SBB32rm, 0 },
676 { X86::SBB64rr, X86::SBB64rm, 0 }, 668 { X86::SBB64rr, X86::SBB64rm, 0 },
677 { X86::SHUFPDrri, X86::SHUFPDrmi, 16 }, 669 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 },
678 { X86::SHUFPSrri, X86::SHUFPSrmi, 16 }, 670 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 },
679 { X86::SUB16rr, X86::SUB16rm, 0 }, 671 { X86::SUB16rr, X86::SUB16rm, 0 },
680 { X86::SUB32rr, X86::SUB32rm, 0 }, 672 { X86::SUB32rr, X86::SUB32rm, 0 },
681 { X86::SUB64rr, X86::SUB64rm, 0 }, 673 { X86::SUB64rr, X86::SUB64rm, 0 },
682 { X86::SUB8rr, X86::SUB8rm, 0 }, 674 { X86::SUB8rr, X86::SUB8rm, 0 },
683 { X86::SUBPDrr, X86::SUBPDrm, 16 }, 675 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 },
684 { X86::SUBPSrr, X86::SUBPSrm, 16 }, 676 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 },
685 { X86::SUBSDrr, X86::SUBSDrm, 0 }, 677 { X86::SUBSDrr, X86::SUBSDrm, 0 },
686 { X86::SUBSSrr, X86::SUBSSrm, 0 }, 678 { X86::SUBSSrr, X86::SUBSSrm, 0 },
687 // FIXME: TEST*rr -> swapped operand of TEST*mr. 679 // FIXME: TEST*rr -> swapped operand of TEST*mr.
688 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, 16 }, 680 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 },
689 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, 16 }, 681 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 },
690 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, 16 }, 682 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 },
691 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, 16 }, 683 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 },
692 { X86::XOR16rr, X86::XOR16rm, 0 }, 684 { X86::XOR16rr, X86::XOR16rm, 0 },
693 { X86::XOR32rr, X86::XOR32rm, 0 }, 685 { X86::XOR32rr, X86::XOR32rm, 0 },
694 { X86::XOR64rr, X86::XOR64rm, 0 }, 686 { X86::XOR64rr, X86::XOR64rm, 0 },
695 { X86::XOR8rr, X86::XOR8rm, 0 }, 687 { X86::XOR8rr, X86::XOR8rm, 0 },
696 { X86::XORPDrr, X86::XORPDrm, 16 }, 688 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 },
697 { X86::XORPSrr, X86::XORPSrm, 16 } 689 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 }
698 }; 690 };
699 691
700 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) { 692 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
701 unsigned RegOp = OpTbl2[i][0]; 693 unsigned RegOp = OpTbl2[i][0];
702 unsigned MemOp = OpTbl2[i][1] & ~TB_FLAGS; 694 unsigned MemOp = OpTbl2[i][1];
703 unsigned Align = OpTbl2[i][2]; 695 unsigned Flags = OpTbl2[i][2];
704 696 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
705 assert(!RegOp2MemOpTable2.count(RegOp) && "Duplicate entry!"); 697 RegOp, MemOp,
706 RegOp2MemOpTable2[RegOp] = std::make_pair(MemOp, Align); 698 // Index 2, folded load
707 699 Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
708 // If this is not a reversible operation (because there is a many->one)
709 // mapping, don't insert the reverse of the operation into MemOp2RegOpTable.
710 if (OpTbl2[i][1] & TB_NOT_REVERSABLE)
711 continue;
712
713 // Index 2, folded load
714 unsigned AuxInfo = 2 | (1 << 4);
715 assert(!MemOp2RegOpTable.count(MemOp) &&
716 "Duplicated entries in unfolding maps?");
717 MemOp2RegOpTable[MemOp] = std::make_pair(RegOp, AuxInfo);
718 } 700 }
719 } 701 }
720 702
703 void
704 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
705 MemOp2RegOpTableType &M2RTable,
706 unsigned RegOp, unsigned MemOp, unsigned Flags) {
707 if ((Flags & TB_NO_FORWARD) == 0) {
708 assert(!R2MTable.count(RegOp) && "Duplicate entry!");
709 R2MTable[RegOp] = std::make_pair(MemOp, Flags);
710 }
711 if ((Flags & TB_NO_REVERSE) == 0) {
712 assert(!M2RTable.count(MemOp) &&
713 "Duplicated entries in unfolding maps?");
714 M2RTable[MemOp] = std::make_pair(RegOp, Flags);
715 }
716 }
717
721 bool 718 bool
722 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI, 719 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
723 unsigned &SrcReg, unsigned &DstReg, 720 unsigned &SrcReg, unsigned &DstReg,
724 unsigned &SubIdx) const { 721 unsigned &SubIdx) const {
725 switch (MI.getOpcode()) { 722 switch (MI.getOpcode()) {
726 default: break; 723 default: break;
727 case X86::MOVSX16rr8: 724 case X86::MOVSX16rr8:
728 case X86::MOVZX16rr8: 725 case X86::MOVZX16rr8:
729 case X86::MOVSX32rr8: 726 case X86::MOVSX32rr8:
730 case X86::MOVZX32rr8: 727 case X86::MOVZX32rr8:
(...skipping 1548 matching lines...) Expand 10 before | Expand all | Expand 10 after
2279 OpcodeTablePtr = &RegOp2MemOpTable2; 2276 OpcodeTablePtr = &RegOp2MemOpTable2;
2280 } 2277 }
2281 2278
2282 // If table selected... 2279 // If table selected...
2283 if (OpcodeTablePtr) { 2280 if (OpcodeTablePtr) {
2284 // Find the Opcode to fuse 2281 // Find the Opcode to fuse
2285 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 2282 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
2286 OpcodeTablePtr->find(MI->getOpcode()); 2283 OpcodeTablePtr->find(MI->getOpcode());
2287 if (I != OpcodeTablePtr->end()) { 2284 if (I != OpcodeTablePtr->end()) {
2288 unsigned Opcode = I->second.first; 2285 unsigned Opcode = I->second.first;
2289 unsigned MinAlign = I->second.second; 2286 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
2290 if (Align < MinAlign) 2287 if (Align < MinAlign)
2291 return NULL; 2288 return NULL;
2292 bool NarrowToMOV32rm = false; 2289 bool NarrowToMOV32rm = false;
2293 if (Size) { 2290 if (Size) {
2294 unsigned RCSize = getRegClass(MI->getDesc(), i, &RI)->getSize(); 2291 unsigned RCSize = getRegClass(MI->getDesc(), i, &RI)->getSize();
2295 if (Size < RCSize) { 2292 if (Size < RCSize) {
2296 // Check if it's safe to fold the load. If the size of the object is 2293 // Check if it's safe to fold the load. If the size of the object is
2297 // narrower than the load width, then it's not. 2294 // narrower than the load width, then it's not.
2298 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4) 2295 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
2299 return NULL; 2296 return NULL;
(...skipping 294 matching lines...) Expand 10 before | Expand all | Expand 10 after
2594 } 2591 }
2595 2592
2596 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 2593 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
2597 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 2594 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
2598 SmallVectorImpl<MachineInstr*> &NewMIs) const { 2595 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2599 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 2596 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
2600 MemOp2RegOpTable.find(MI->getOpcode()); 2597 MemOp2RegOpTable.find(MI->getOpcode());
2601 if (I == MemOp2RegOpTable.end()) 2598 if (I == MemOp2RegOpTable.end())
2602 return false; 2599 return false;
2603 unsigned Opc = I->second.first; 2600 unsigned Opc = I->second.first;
2604 unsigned Index = I->second.second & 0xf; 2601 unsigned Index = I->second.second & TB_INDEX_MASK;
2605 bool FoldedLoad = I->second.second & (1 << 4); 2602 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
2606 bool FoldedStore = I->second.second & (1 << 5); 2603 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
2607 if (UnfoldLoad && !FoldedLoad) 2604 if (UnfoldLoad && !FoldedLoad)
2608 return false; 2605 return false;
2609 UnfoldLoad &= FoldedLoad; 2606 UnfoldLoad &= FoldedLoad;
2610 if (UnfoldStore && !FoldedStore) 2607 if (UnfoldStore && !FoldedStore)
2611 return false; 2608 return false;
2612 UnfoldStore &= FoldedStore; 2609 UnfoldStore &= FoldedStore;
2613 2610
2614 const MCInstrDesc &MCID = get(Opc); 2611 const MCInstrDesc &MCID = get(Opc);
2615 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI); 2612 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI);
2616 if (!MI->hasOneMemOperand() && 2613 if (!MI->hasOneMemOperand() &&
(...skipping 105 matching lines...) Expand 10 before | Expand all | Expand 10 after
2722 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 2719 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
2723 SmallVectorImpl<SDNode*> &NewNodes) const { 2720 SmallVectorImpl<SDNode*> &NewNodes) const {
2724 if (!N->isMachineOpcode()) 2721 if (!N->isMachineOpcode())
2725 return false; 2722 return false;
2726 2723
2727 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 2724 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
2728 MemOp2RegOpTable.find(N->getMachineOpcode()); 2725 MemOp2RegOpTable.find(N->getMachineOpcode());
2729 if (I == MemOp2RegOpTable.end()) 2726 if (I == MemOp2RegOpTable.end())
2730 return false; 2727 return false;
2731 unsigned Opc = I->second.first; 2728 unsigned Opc = I->second.first;
2732 unsigned Index = I->second.second & 0xf; 2729 unsigned Index = I->second.second & TB_INDEX_MASK;
2733 bool FoldedLoad = I->second.second & (1 << 4); 2730 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
2734 bool FoldedStore = I->second.second & (1 << 5); 2731 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
2735 const MCInstrDesc &MCID = get(Opc); 2732 const MCInstrDesc &MCID = get(Opc);
2736 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI); 2733 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI);
2737 unsigned NumDefs = MCID.NumDefs; 2734 unsigned NumDefs = MCID.NumDefs;
2738 std::vector<SDValue> AddrOps; 2735 std::vector<SDValue> AddrOps;
2739 std::vector<SDValue> BeforeOps; 2736 std::vector<SDValue> BeforeOps;
2740 std::vector<SDValue> AfterOps; 2737 std::vector<SDValue> AfterOps;
2741 DebugLoc dl = N->getDebugLoc(); 2738 DebugLoc dl = N->getDebugLoc();
2742 unsigned NumOps = N->getNumOperands(); 2739 unsigned NumOps = N->getNumOperands();
2743 for (unsigned i = 0; i != NumOps-1; ++i) { 2740 for (unsigned i = 0; i != NumOps-1; ++i) {
2744 SDValue Op = N->getOperand(i); 2741 SDValue Op = N->getOperand(i);
(...skipping 77 matching lines...) Expand 10 before | Expand all | Expand 10 after
2822 return true; 2819 return true;
2823 } 2820 }
2824 2821
2825 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, 2822 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
2826 bool UnfoldLoad, bool UnfoldStore, 2823 bool UnfoldLoad, bool UnfoldStore,
2827 unsigned *LoadRegIndex) const { 2824 unsigned *LoadRegIndex) const {
2828 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 2825 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
2829 MemOp2RegOpTable.find(Opc); 2826 MemOp2RegOpTable.find(Opc);
2830 if (I == MemOp2RegOpTable.end()) 2827 if (I == MemOp2RegOpTable.end())
2831 return 0; 2828 return 0;
2832 bool FoldedLoad = I->second.second & (1 << 4); 2829 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
2833 bool FoldedStore = I->second.second & (1 << 5); 2830 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
2834 if (UnfoldLoad && !FoldedLoad) 2831 if (UnfoldLoad && !FoldedLoad)
2835 return 0; 2832 return 0;
2836 if (UnfoldStore && !FoldedStore) 2833 if (UnfoldStore && !FoldedStore)
2837 return 0; 2834 return 0;
2838 if (LoadRegIndex) 2835 if (LoadRegIndex)
2839 *LoadRegIndex = I->second.second & 0xf; 2836 *LoadRegIndex = I->second.second & TB_INDEX_MASK;
2840 return I->second.first; 2837 return I->second.first;
2841 } 2838 }
2842 2839
2843 bool 2840 bool
2844 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 2841 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
2845 int64_t &Offset1, int64_t &Offset2) const { 2842 int64_t &Offset1, int64_t &Offset2) const {
2846 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 2843 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
2847 return false; 2844 return false;
2848 unsigned Opc1 = Load1->getMachineOpcode(); 2845 unsigned Opc1 = Load1->getMachineOpcode();
2849 unsigned Opc2 = Load2->getMachineOpcode(); 2846 unsigned Opc2 = Load2->getMachineOpcode();
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3196 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 3193 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
3197 AU.setPreservesCFG(); 3194 AU.setPreservesCFG();
3198 MachineFunctionPass::getAnalysisUsage(AU); 3195 MachineFunctionPass::getAnalysisUsage(AU);
3199 } 3196 }
3200 }; 3197 };
3201 } 3198 }
3202 3199
3203 char CGBR::ID = 0; 3200 char CGBR::ID = 0;
3204 FunctionPass* 3201 FunctionPass*
3205 llvm::createGlobalBaseRegPass() { return new CGBR(); } 3202 llvm::createGlobalBaseRegPass() { return new CGBR(); }
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