MIPS: port ARM: Fix context save/restore for VFP registers.

src/mips/macro-assembler-mips.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
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@@ skipping 734 matching lines @@
 
   for (int16_t i = kNumRegisters; i > 0; i--) {
     if ((regs & (1 << i)) != 0) {
       lw(ToRegister(i), MemOperand(sp, 4 * (NumSaved++)));
     }
   }
   addiu(sp, sp, 4 * NumSaved);
 }
 
 
+void MacroAssembler::MultiPushFPU(RegList regs) {
+  CpuFeatures::Scope scope(FPU);
+  int16_t NumSaved = 0;
+  int16_t NumToPush = NumberOfBitsSet(regs);
+
+  addiu(sp, sp, -8 * NumToPush);
+  for (int16_t i = kNumRegisters; i > 0; i--) {
+    if ((regs & (1 << i)) != 0) {
+      sdc1(FPURegister::from_code(i),
+           MemOperand(sp, 8 * (NumToPush - ++NumSaved)));
+    }
+  }

[Yang, 2011/08/31 12:38:44]

Consider - for readability - introducing a stack_offset variable to keep track
where to store the next register. For example:

int16_t NumToPush = NumberOfBitsSet(regs);
int16_t stack_offset = NumToPush * 8;

addiu(sp, sp, -8 * NumToPush);
for (int16_t i = kNumRegisters; i > 0; i--) {
  if ((regs & (1 << i)) != 0) {
    stack_offset -= 8;
    sdc1(FPURegister::from_code(i),
         MemOperand(sp, stack_offset));
  }
}

Also consider using kDoubleSize instead of the constant 8.

Maybe those non-FPU MultiPush and MultiPop commands can be refactored as well?

[Paul Lind, 2011/09/01 06:50:27]

Nice suggestion, the code looks much cleaner now. I updated all the Multi's ...

BTW, mips does not have a subiu instruction. The addiu takes a signed 16-bit
immediate, so it can be used for subtract. I changed to use the Subu()
macro-instruction, which emits addiu with negative immediate value, to make it
more obvious in the code we are subtracting (more obvious than - sign.)

+}
+
+
+void MacroAssembler::MultiPushReversedFPU(RegList regs) {
+  CpuFeatures::Scope scope(FPU);
+  int16_t NumSaved = 0;
+  int16_t NumToPush = NumberOfBitsSet(regs);
+
+  addiu(sp, sp, -8 * NumToPush);
+  for (int16_t i = 0; i < kNumRegisters; i++) {
+    if ((regs & (1 << i)) != 0) {
+      sdc1(FPURegister::from_code(i),
+           MemOperand(sp, 8 * (NumToPush - ++NumSaved)));
+    }
+  }
+}
+
+
+void MacroAssembler::MultiPopFPU(RegList regs) {
+  CpuFeatures::Scope scope(FPU);
+  int16_t NumSaved = 0;
+
+  for (int16_t i = 0; i < kNumRegisters; i++) {
+    if ((regs & (1 << i)) != 0) {
+      ldc1(FPURegister::from_code(i),
+           MemOperand(sp, 8 * (NumSaved++)));
+    }
+  }
+  addiu(sp, sp, 8 * NumSaved);
+}
+
+
+void MacroAssembler::MultiPopReversedFPU(RegList regs) {
+  CpuFeatures::Scope scope(FPU);
+  int16_t NumSaved = 0;
+
+  for (int16_t i = kNumRegisters; i > 0; i--) {
+    if ((regs & (1 << i)) != 0) {
+      ldc1(FPURegister::from_code(i),
+           MemOperand(sp, 8 * (NumSaved++)));
+    }
+  }
+  addiu(sp, sp, 8 * NumSaved);
+}
+
+
 void MacroAssembler::Ext(Register rt,
                          Register rs,
                          uint16_t pos,
                          uint16_t size) {
   ASSERT(pos < 32);
   ASSERT(pos + size < 33);
 
   if (mips32r2) {
     ext_(rt, rs, pos, size);
   } else {
@@ skipping 3540 matching lines @@
        opcode == BGTZL);
   opcode = (cond == eq) ? BEQ : BNE;
   instr = (instr & ~kOpcodeMask) | opcode;
   masm_.emit(instr);
 }
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_MIPS