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Issue 7799013:
Intial Thumb2 Sandbox (naclrev 6680)
Base URL: svn://svn.chromium.org/native_client/trunk/src/native_client| OLD | NEW |
|---|---|
| (Empty) | |
| 1 # ARMv7 Instruction Encodings | |
| 2 # | |
| 3 # This table is derived from the "ARM Architecture Reference Manual, ARMv7-A | |
| 4 # and ARMv7-R edition" and is used here with the permission of ARM Limited. | |
| 5 # Reproduction for purposes other than the development and distribution of | |
| 6 # Native Client may require the explicit permission of ARM Limited. | |
|
bsy
2011/09/01 00:30:00
how was this obtained? it's great that this is da
jasonwkim
2011/09/16 20:09:16
For ARM mode, we are pretty assured. For thunb2, i
| |
| 7 | |
| 8 # This file defines the Native Client "instruction classes" assigned to every | |
| 9 # possible ARMv7 instruction encoding. It is organized into a series of tables, | |
| 10 # and directly parallels the ARM Architecture Reference Manual cited above. | |
| 11 # | |
| 12 # Each table consists of | |
| 13 # - A name, | |
| 14 # - A citation in the Architecture Reference Manual, | |
| 15 # - One or more columns defining bitfields to match, and | |
| 16 # - One or more rows describing patterns in those bitfields. | |
| 17 # | |
| 18 # A leading tilde (~) negates a pattern. A hyphen (-) is short for a string of | |
| 19 # don't-care bits (x). A double-quote (") indicates that a pattern is the same | |
| 20 # as the row above it. | |
| 21 # | |
| 22 # Each row may specify a terminal instruction class ("=InstClass"), or forward | |
| 23 # the reader to a different table ("->table_name"). | |
| 24 # | |
| 25 # If an encoding is not valid in every ARM architecture rev, the instruction | |
| 26 # class may indicate the rev or feature that makes the encoding valid in | |
| 27 # parentheses. | |
| 28 # | |
| 29 # This table is for the decoding of Thumb mode instructions. | |
| 30 | |
| 31 -- ARMv7_Thumb (See Section A6.1) | |
| 32 bittage(15:11) | |
| 33 11101 ->thumb32 #(v6T2) | |
| 34 11110 " | |
| 35 11111 " | |
| 36 - ->thumb16 | |
| 37 | |
| 38 -- thumb16 (See Section A6.2) | |
| 39 opcode(15:10) | |
| 40 00xxxx ->dp_shifted_imm | |
| 41 010000 ->dp | |
| 42 010001 ->special_and_bx | |
| 43 01001x =LDRLitT1(v4T) # LDR (literal) T1 A8-122 | |
| 44 0101xx ->ldst_single | |
| 45 011xxx " | |
| 46 100xxx " | |
| 47 10100x =ADRT1(v4T) # ADR T1 A8-32 | |
| 48 10101x =SPMod(v4T) # ADD (SP plus immediate) T1 A8-28 | |
| 49 1011xx ->misc16 | |
| 50 11000x =STMT1(v4T) # STM* T1 A8-374 | |
| 51 11001x =LDMT1(v4T) # LDM* T1 A8-110 | |
| 52 1101xx ->cond_br_and_svc | |
| 53 11100x =BranchT2(v4T) # B T2 A8-44 | |
| 54 | |
| 55 -- dp_shifted_imm (See Section A6.2.1) | |
| 56 opcode(13:9) | |
| 57 000xx =Def3 # LSL (immediate) T1 A8-178 | |
| 58 001xx =Def3 # LSR (immediate) T1 A8-182 | |
| 59 010xx =Def3 # ASR (immediate) T1 A8-40 | |
| 60 01100 =Def3 # ADD (register) T1 A8-24 | |
| 61 01101 =Def3 # SUB (register) T1 A8-422 | |
| 62 01110 =Def3 # ADD (immediate, 3-bit) T1 A8-20 | |
| 63 01111 =Def3 # SUB (immediate, 3-bit) T1 A8-418 | |
| 64 100xx =Def8_10 # MOV (immediate) T1 A8-194 | |
| 65 101xx =Cmp # CMP (immediate) T1 A8-80 | |
| 66 110xx =Def8_10 # ADD (immediate, 8-bit) T2 A8-20 | |
| 67 111xx =Def8_10 # SUB (immediate, 8-bit) T2 A8-418 | |
| 68 | |
| 69 -- dp (See Section A6.2.2) | |
| 70 opcode(9:6) | |
| 71 0000 =Mask3 # AND (register) T1 A8-36 | |
| 72 0001 =Def3 # EOR (register) T1 A8-96 | |
| 73 0010 =Def3 # LSL (register) T1 A8-180 | |
| 74 0011 =Def3 # LSR (register) T1 A8-184 | |
| 75 0100 =Def3 # ASR (register) T1 A8-42 | |
| 76 0101 =Def3 # ADC (register) T1 A8-16 | |
| 77 0110 =Def3 # SBC (register) T1 A8-304 | |
| 78 0111 =Def3 # ROR (register) T1 A8-280 | |
| 79 1000 =Cmp # TST (register) T1 A8-456 | |
| 80 1001 =Def3 # RSB (immediate) T1 A8-284 | |
| 81 1010 =Cmp # CMP (high register) T1 A8-82 | |
| 82 1011 =Cmp # CMN (register) T1 A8-76 | |
| 83 1100 =OrMask3 # ORR (register) T1 A8-230 | |
| 84 1101 =Def3 # MUL T1 A8-212 | |
| 85 1110 =BiC3 # BIC (register) T1 A8-52 | |
| 86 1111 =Def3 # MVN T1 A8-216 | |
| 87 | |
| 88 -- special_and_bx (See Section A6.2.3) | |
| 89 opcode(9:6) safety(2:0) | |
| 90 0000 - =Def3(v6T2) # ADD (low register) T2 A8-24 | |
| 91 0001 - =Def3(v4T) # ADD (high register) T2 A8-24 | |
| 92 001x - " | |
| 93 0100 - =Unpredictable | |
| 94 0101 - =Cmp(v4T) # CMP (high register) T2 A8-82 | |
| 95 011x - " | |
| 96 1000 - =MovT(v6) # MOV (low register) T1 A8-196 | |
| 97 1001 - =MovT(v4T) # MOV (high register) T1 A8-196 | |
| 98 101x - " | |
| 99 110x - =BXT(v4T) # BX T1 A8-62 | |
| 100 111x 000 =BLXT(v5T) # BLX (register) T1 A8-60 | |
| 101 | |
| 102 -- ldst_single (See Section A6.2.4) | |
| 103 opA(15:12) opB(11:9) | |
| 104 0101 000 =MemOpThumbStore # STR (register) | |
| 105 " 001 " # STRH (register) | |
| 106 " 010 " # STRB (register) | |
| 107 " 011 =MemOpThumbLoad # LDRSB (register) | |
| 108 " 100 " # LDR (register) | |
| 109 " 101 " # LDRH (register) | |
| 110 " 110 " # LDRB (register) | |
| 111 " 111 " # LDRSH (register) | |
| 112 0110 0xx =MemOpThumbStore # STR (immediate) | |
| 113 0111 " " # STRB (immediate) | |
| 114 1000 " " # STRH (immediate) | |
| 115 0110 1xx =MemOpThumbLoad # LDR (immediate) | |
| 116 0111 " " # LDRB (immediate) | |
| 117 1000 " " # LDRH (immediate) | |
| 118 1001 0xx =MemOpSPThumbStore # STR (immediate, SP Relative) | |
| 119 1001 1xx =MemOpSPThumbLoad # LDR (immediate, SP Relative) | |
| 120 | |
| 121 -- misc16 (See Section A6.2.5) | |
| 122 opcode(11:5) | |
| 123 0110010 =Forbidden(v6) # SETEND | |
| 124 0110011 =Forbidden(v6) # CPS | |
| 125 00000xx =SPMod(v4T) # ADD (SP plus immediate) | |
| 126 00001xx =SPMod(v4T) # SUB (SP minus immediate) | |
| 127 0001xxx =CmpBrZ(v6T2) # CBNZ, CBZ | |
| 128 0011xxx " | |
| 129 1001xxx " | |
| 130 1011xxx " | |
| 131 001000x =Def3(v6) # SXTH | |
| 132 001001x " # SXTB | |
| 133 001010x " # UXTH | |
| 134 001011x " # UXTB | |
| 135 101000x " # REV | |
| 136 101001x " # REV16 | |
| 137 101011x " # REVSH | |
| 138 010xxxx =PushMult(v4T) # PUSH | |
| 139 110xxxx =PopMult(v4T) # POP | |
| 140 1110xxx =ThumbBreakpoint(v5) # BPKT | |
| 141 1111xxx ->it_and_hints | |
| 142 | |
| 143 -- it_and_hints (See Section A6.2.5 subsection) | |
| 144 opA(7:4) opB(3:0) | |
| 145 - ~0000 =IT(v6T2) # IT | |
| 146 0000 0000 =EffectiveNoOp(v6T2) # NOP | |
| 147 0001 0000 =Forbidden(v7) # YIELD | |
| 148 0010 0000 " # WFE | |
| 149 0011 0000 " # WFI | |
| 150 0100 0000 " # SEV | |
| 151 | |
| 152 -- cond_br_and_svc (See Section A6.2.6) | |
| 153 opcode(11:8) | |
| 154 ~111x =BranchT2 # B | |
| 155 1110 =Undefined | |
| 156 1111 =Forbidden # SVC/SWI | |
| 157 | |
| 158 -- thumb32 (See Section A6.3) | |
| 159 op1(12:11) op2(10:4) op(31) | |
| 160 01 00xx0xx - ->ldstm # (v6T2) | |
| 161 " 00xx1xx - ->ldstduex_and_tbr | |
| 162 " 01xxxxx - ->dp_shifted_reg | |
| 163 " 1xxxxxx - ->coprocessor | |
| 164 10 x0xxxxx 0 ->dp_mod_imm | |
| 165 " x1xxxxx 0 ->dp_imm | |
| 166 " - 1 ->br_misc | |
| 167 11 000xxx0 - ->st_single | |
| 168 " 001xxx0 - ->asimd | |
| 169 " 00xx001 - ->ldb_and_hint | |
| 170 " 00xx011 - ->ldh_and_hint | |
| 171 " 00xx101 - ->ldw | |
| 172 " 00xx111 - =Undefined | |
| 173 " 010xxxx - ->dp_reg | |
| 174 " 0110xxx - ->math | |
| 175 " 0111xxx - ->math2 | |
| 176 " 1xxxxxx - ->coprocessor2 | |
| 177 | |
| 178 -- dp_mod_imm (See Section A6.3.1) | |
| 179 op(8:5) Rn(3:0) Rd(27:24) S(4:4) | |
| 180 0000 - ~1111 x =DPMImm # AND (immediate) | |
| 181 " - 1111 0 =Unpredictable | |
| 182 " - 1111 1 =Cmp # TST (immediate) | |
| 183 0001 - - - =BicModImmT # BIC (immediate) | |
| 184 0010 ~1111 - - =OrrModImmT # ORR (immediate) | |
| 185 " 1111 - - =DPMImm # MOV (immediate) | |
| 186 0011 ~1111 - - =DPMImm # ORN (immediate) | |
| 187 " 1111 - - =DPMImm # MVN (immediate) | |
| 188 0100 - ~1111 x =DPMImm # EOR (immediate) | |
| 189 " - 1111 0 =Unpredictable | |
| 190 " - " 1 =Cmp # TEQ (immediate) | |
| 191 1000 - ~1111 x =DPMImm # ADD (immediate) | |
| 192 " - 1111 0 =Unpredictable | |
| 193 " - " 1 =Cmp # CMN (immediate) | |
| 194 1010 - - - =DPMImm # ADC (immediate) | |
| 195 1011 - - - =DPMImm # SBC (immediate) | |
| 196 1101 - ~1111 - =DPMImm # SUB (immediate) | |
| 197 " - 1111 0 =Unpredictable | |
| 198 " - " 1 =Cmp # CMP (immediate) | |
| 199 1110 - - - =DPMImm # RSB (immediate) | |
| 200 | |
| 201 -- dp_imm (See Section A6.3.3) | |
| 202 op(8:4) Rn(3:0) safety(30:22) | |
| 203 00000 ~1111 - =DPMImm # ADD (immediate) | |
| 204 " 1111 - =DPMImm # ADR (immediate) | |
| 205 00100 - - =DPMImm # MOV (immediate) | |
| 206 01010 ~1111 - =DPMImm # SUB (immediate) | |
| 207 " 1111 - =DPMImm # ADR (immediate) | |
| 208 01100 - - =DPMImm # MOVT (immediate) | |
| 209 100x0 - ~000xxxx00 =DPMImm # SSAT (immediate) | |
| 210 10010 - 000xxxx00 =DPMImm # SSAT16 (immediate) | |
| 211 10100 - - =DPMImm # SBFX (immediate) | |
| 212 10110 ~1111 - =DPMImm # BFI | |
| 213 " 1111 - =DPMImm # BFC | |
| 214 110x0 - ~000xxxx00 =DPMImm # USAT | |
| 215 11010 - 000xxxx00 =DPMImm # USAT16 | |
| 216 11100 - - =DPMImm # UBFX | |
| 217 | |
| 218 -- br_misc (See Section A6.3.4-1) | |
| 219 op1(30:28) op(10:4) op2(27:24) | |
| 220 0x0 ~x111xxx - =BranchT3(v6T2) # B | |
| 221 " 0111000 xx00 =Forbidden # MSR (App) | |
| 222 " " xx01 =Forbidden # MSR (Sys) | |
| 223 " " xx1x " | |
| 224 " 0111001 - " | |
| 225 " 0111010 - ->cps_and_hints | |
| 226 " 0111011 - ->misc_ctl | |
| 227 " 0111100 - =Forbidden(v6T2) # BXJ | |
| 228 " 0111101 - =Unimplemented(v6T2) # SUBS PC, LR, #const | |
| 229 " 011111x - =Forbidden(v6T2) # MRS | |
| 230 000 1111111 - =Forbidden # SMC/SMI | |
| 231 010 1111111 - =Undefined | |
| 232 0x1 - - =BranchT4(v6T2) # B | |
| 233 1x0 - - =Forbidden(v5T) # BLX | |
| 234 1x1 - - =BLT # BL | |
| 235 | |
| 236 -- cps_and_hints (See Section A6.3.4-2) | |
| 237 op1(26:24) op2(23:16) | |
| 238 ~000 - =Forbidden(v6T2) # CPS | |
| 239 000 00000000 =EffectiveNoOp(v6T2) # NOP | |
| 240 " 00000001 =Forbidden # YIELD | |
| 241 " 00000010 " # WFE | |
| 242 " 00000011 " # WFI | |
| 243 " 00000100 " # SEV | |
| 244 " 1111xxxx " # DBG | |
| 245 | |
| 246 -- misc_ctl (See Section A6.3.4-3) | |
| 247 op(23:20) | |
| 248 0000 =Forbidden # ENTERX | |
| 249 0001 =Forbidden # LEAVEX | |
| 250 0010 =EffectiveNoOp(v7) # CLREX | |
| 251 0011 " # DSB | |
| 252 0101 " # DMB | |
| 253 0110 " # ISB | |
| 254 | |
| 255 -- ldstm (See Section A6.3.5) | |
| 256 op(8:7) L(4:4) Rn(3:0) | |
| 257 00 0 - =Forbidden # SRS | |
| 258 " 1 - =Forbidden # RFE | |
| 259 01 0 - =STMTD # STM/IA/EA | |
| 260 " 1 ~1101 =LDMTD # LDM/IA/EA | |
| 261 " " 1101 =LDMTD # POP | |
| 262 10 0 ~1101 =STMTD # STMDB/FD | |
| 263 " " 1101 =STMTD # PUSH | |
| 264 " 1 - =LDMTD # LDMDB/FD | |
| 265 11 0 - =Forbidden # SRS | |
| 266 " 1 - =Forbidden # RFE | |
| 267 | |
| 268 -- ldstduex_and_tbr (See A6.3.6) | |
| 269 op1(8:7) op2(5:4) op3(23:20) Rn(3:0) | |
| 270 00 00 - - =StrEx # STREX | |
| 271 " 01 - - =LdrEx # LDREX | |
| 272 0x 10 - - =StrS # STRD | |
| 273 1x x0 " " " | |
| 274 0x 11 - ~1111 =LdrD # LDRD | |
| 275 1x x1 - " " | |
| 276 0x 11 - 1111 =Forbidden | |
| 277 # I am banning this because it appears to cause a decode loop in the spec | |
| 278 # On actual CPUs, this seems to cause an Illegal Instruction exception. | |
| 279 1x 01 - 1111 =LdrD # LDRD literal (e.g. constpool) | |
| 280 # Note, I have forced a bit here to prevent us from leaving spec land. The spec | |
| 281 # is not self consistent. A8.6.67 contradicts this line in the table, and I'm | |
| 282 # trusting it, as it was a marked up change | |
| 283 01 00 0100 - =StrEx # STREXB | |
| 284 " " 0101 - " # STREXH | |
| 285 " " 0111 - =StrExD # STREXD | |
| 286 " 01 0000 - =Forbidden # TBB # Bundle size needs to be | |
| 287 " " 0001 - " # TBH # at least 18 to implement | |
| 288 # or we need masking logic | |
| 289 " " 0100 - =LdrEx # LDREXB | |
| 290 " " 0101 - " # LDREXH | |
| 291 " " 0111 - =LdrExD # LDREXD | |
| 292 | |
| 293 -- ldw (A6.3.7) | |
| 294 op1(8:7) op2(27:22) Rn(3:0) | |
| 295 01 - ~1111 =LDRImmT3 # LDR | |
| 296 00 1xx1xx " =LDRImmT4 | |
| 297 " 1100xx " " | |
| 298 " 1110xx " " # LDRT | |
| 299 " 000000 " " # LDR | |
| 300 0x - 1111 =Def31_18 # LDR | |
| 301 | |
| 302 -- ldh_and_hint (A6.3.8) | |
| 303 op1(8:7) op2(27:22) Rn(3:0) Rt(31:28) | |
| 304 0x - 1111 ~1111 =LDRImmT3 # LDRH | |
| 305 01 - ~1111 1111 " | |
| 306 00 1xx1xx ~1111 ~1111 =LDRImmT4 | |
| 307 " 1100xx " " =LDRImmT3 | |
| 308 " 1110xx " " " # LDRHT | |
| 309 " 000000 " " " # LDRH | |
| 310 1x - 1111 ~1111 " # LDRSH | |
| 311 11 - ~1111 1111 " | |
| 312 10 1xx1xx ~1111 ~1111 =LDRImmT4 | |
| 313 " 1100xx " " =LDRImmT3 | |
| 314 " 1110xx " " " # LDRSHT | |
| 315 " 000000 " " " # LDRSH | |
| 316 0x - 1111 1111 =Unpredictable | |
| 317 01 - ~1111 1111 =EffectiveNoOp # PLD/PLDW | |
| 318 00 1100xx ~1111 1111 " | |
| 319 " 000000 ~1111 1111 " | |
| 320 00 1xx1xx ~1111 1111 =Unpredictable | |
| 321 " 1110xx ~1111 1111 " | |
| 322 1x - 1111 1111 =EffectiveNoOp # Unallocated hint | |
| 323 10 1100xx ~1111 1111 " | |
| 324 " 000000 ~1111 1111 " | |
| 325 " 1xx1xx " " =Unpredictable | |
| 326 " 1110xx " " " | |
| 327 11 - " " =EffectiveNoOp # Unallocated hint | |
| 328 | |
| 329 -- ldb_and_hint (A.6.3.9) | |
| 330 op1(8:7) op2(27:22) Rn(3:0) Rt(31:28) | |
| 331 0x - 1111 ~1111 =LDRImmT3 # LDRB | |
| 332 01 - ~1111 1111 " | |
| 333 00 1xx1xx ~1111 ~1111 =LDRImmT4 | |
| 334 " 1100xx " " =LDRImmT3 | |
| 335 " 1110xx " " " # LDRBT | |
| 336 " 000000 " " " # LDRB | |
| 337 1x - 1111 ~1111 " # LDRSB | |
| 338 11 - ~1111 1111 " | |
| 339 10 1xx1xx ~1111 ~1111 =LDRImmT4 | |
| 340 " 1100xx " " =LDRImmT3 | |
| 341 " 1110xx " " " # LDRSBT | |
| 342 " 000000 " " " # LDRSB | |
| 343 0x - 1111 1111 =EffectiveNoOp # PLD | |
| 344 01 - ~1111 1111 =EffectiveNoOp # PLD/PLDW | |
| 345 00 1100xx ~1111 1111 " | |
| 346 " 000000 ~1111 1111 " | |
| 347 00 1xx1xx ~1111 1111 =Unpredictable | |
| 348 " 1110xx ~1111 1111 " | |
| 349 1x - 1111 1111 =EffectiveNoOp # PLI | |
| 350 11 - " " " | |
| 351 10 1100xx ~1111 1111 " | |
| 352 " 000000 ~1111 1111 " | |
| 353 " 1xx1xx " " =Unpredictable | |
| 354 " 1110xx " " " | |
| 355 | |
| 356 -- st_single (A6.3.10) | |
| 357 op1(7:5) op2(27:22) | |
| 358 100 - =StrS # STRB | |
| 359 000 1xx1xx " | |
| 360 " 1100xx " | |
| 361 " 1110xx " # STRBT | |
| 362 " 0xxxxx " # STRB | |
| 363 101 - " # STRH | |
| 364 001 1xx1xx " | |
| 365 " 1100xx " | |
| 366 " 1110xx " # STRHT | |
| 367 " 0xxxxx " # STRH | |
| 368 110 - " # STR | |
| 369 010 1xx1xx " | |
| 370 " 1100xx " | |
| 371 " 1110xx " # STRT | |
| 372 " 0xxxxx " # STR | |
| 373 | |
| 374 -- dp_shifted_reg (A6.3.11) | |
| 375 op(8:5) Rn(3:0) Rd(27:24) S(4:4) | |
| 376 0000 - ~1111 x =Def27_24 # AND | |
| 377 " " 1111 0 =Unpredictable | |
| 378 " " " 1 =Cmp # TST | |
| 379 0001 - - - =Def27_24 # BIC | |
| 380 0010 ~1111 - - =Def27_24 # ORR | |
| 381 " 1111 - - =Def27_24 # MOV | |
| 382 0011 ~1111 - - =Def27_24 # ORN | |
| 383 " 1111 - - =Def27_24 # MVN | |
| 384 0100 ~1111 - - =Def27_24 # EOR | |
| 385 " 1111 - 0 =Unpredictable | |
| 386 " " - 1 =Cmp # TEQ | |
| 387 0110 - - - =Def27_24 # PKH | |
| 388 1000 ~1111 - - =Def27_24 # ADD | |
| 389 " 1111 - 0 =Unpredictable | |
| 390 " " - 1 =Cmp # CMN | |
| 391 1010 - - - =Def27_24 # ADC | |
| 392 1011 - - - =Def27_24 # SBC | |
| 393 1101 ~1111 - - =Def27_24 # SUB | |
| 394 " 1111 - 0 =Unpredictable | |
| 395 " " - 1 =Cmp # CMP | |
| 396 1011 - - - =Def27_24 # RSB | |
| 397 | |
| 398 | |
| 399 -- coprocessor ( ) | |
| 400 op(0:0) | |
| 401 - =Unimplemented | |
| 402 | |
| 403 -- asimd ( ) | |
| 404 op(0:0) | |
| 405 - =Unimplemented | |
| 406 | |
| 407 -- dp_reg ( ) | |
| 408 op(0:0) | |
| 409 - =Unimplemented | |
| 410 | |
| 411 -- math ( ) | |
| 412 op(0:0) | |
| 413 - =Unimplemented | |
| 414 | |
| 415 -- math2 ( ) | |
| 416 op(0:0) | |
| 417 - =Unimplemented | |
| 418 | |
| 419 -- coprocessor2 ( ) | |
| 420 op(0:0) | |
| 421 - =Unimplemented | |
| OLD | NEW |
