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| 1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. | 
| 2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without | 
| 3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are | 
| 4 // met: | 4 // met: | 
| 5 // | 5 // | 
| 6 //     * Redistributions of source code must retain the above copyright | 6 //     * Redistributions of source code must retain the above copyright | 
| 7 //       notice, this list of conditions and the following disclaimer. | 7 //       notice, this list of conditions and the following disclaimer. | 
| 8 //     * Redistributions in binary form must reproduce the above | 8 //     * Redistributions in binary form must reproduce the above | 
| 9 //       copyright notice, this list of conditions and the following | 9 //       copyright notice, this list of conditions and the following | 
| 10 //       disclaimer in the documentation and/or other materials provided | 10 //       disclaimer in the documentation and/or other materials provided | 
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| 758                          uint16_t size) { | 758                          uint16_t size) { | 
| 759   ASSERT(pos < 32); | 759   ASSERT(pos < 32); | 
| 760   ASSERT(pos + size < 33); | 760   ASSERT(pos + size < 33); | 
| 761 | 761 | 
| 762   if (mips32r2) { | 762   if (mips32r2) { | 
| 763     ext_(rt, rs, pos, size); | 763     ext_(rt, rs, pos, size); | 
| 764   } else { | 764   } else { | 
| 765     // Move rs to rt and shift it left then right to get the | 765     // Move rs to rt and shift it left then right to get the | 
| 766     // desired bitfield on the right side and zeroes on the left. | 766     // desired bitfield on the right side and zeroes on the left. | 
| 767     int shift_left = 32 - (pos + size); | 767     int shift_left = 32 - (pos + size); | 
| 768     if (shift_left > 0) { | 768     sll(rt, rs, shift_left);  // Acts as a move if shift_left == 0. | 
| 769       sll(rt, rs, shift_left); |  | 
| 770     } |  | 
| 771 | 769 | 
| 772     int shift_right = 32 - size; | 770     int shift_right = 32 - size; | 
| 773     if (shift_right > 0) { | 771     if (shift_right > 0) { | 
| 774       srl(rt, rt, shift_right); | 772       srl(rt, rt, shift_right); | 
| 775     } | 773     } | 
| 776   } | 774   } | 
| 777 } | 775 } | 
| 778 | 776 | 
| 779 | 777 | 
| 780 void MacroAssembler::Ins(Register rt, | 778 void MacroAssembler::Ins(Register rt, | 
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| 4297        opcode == BGTZL); | 4295        opcode == BGTZL); | 
| 4298   opcode = (cond == eq) ? BEQ : BNE; | 4296   opcode = (cond == eq) ? BEQ : BNE; | 
| 4299   instr = (instr & ~kOpcodeMask) | opcode; | 4297   instr = (instr & ~kOpcodeMask) | opcode; | 
| 4300   masm_.emit(instr); | 4298   masm_.emit(instr); | 
| 4301 } | 4299 } | 
| 4302 | 4300 | 
| 4303 | 4301 | 
| 4304 } }  // namespace v8::internal | 4302 } }  // namespace v8::internal | 
| 4305 | 4303 | 
| 4306 #endif  // V8_TARGET_ARCH_MIPS | 4304 #endif  // V8_TARGET_ARCH_MIPS | 
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