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| 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
| 2 // All Rights Reserved. | 2 // All Rights Reserved. |
| 3 // | 3 // |
| 4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
| 5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
| 6 // are met: | 6 // are met: |
| 7 // | 7 // |
| 8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
| 9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
| 10 // | 10 // |
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| 370 | 370 |
| 371 // ----------------------------------------------------------------------------- | 371 // ----------------------------------------------------------------------------- |
| 372 // Machine instruction Operands | 372 // Machine instruction Operands |
| 373 | 373 |
| 374 // Class Operand represents a shifter operand in data processing instructions | 374 // Class Operand represents a shifter operand in data processing instructions |
| 375 class Operand BASE_EMBEDDED { | 375 class Operand BASE_EMBEDDED { |
| 376 public: | 376 public: |
| 377 // immediate | 377 // immediate |
| 378 INLINE(explicit Operand(int32_t immediate, | 378 INLINE(explicit Operand(int32_t immediate, |
| 379 RelocInfo::Mode rmode = RelocInfo::NONE)); | 379 RelocInfo::Mode rmode = RelocInfo::NONE)); |
| 380 INLINE(static Operand Zero()) { |
| 381 return Operand(static_cast<int32_t>(0)); |
| 382 } |
| 380 INLINE(explicit Operand(const ExternalReference& f)); | 383 INLINE(explicit Operand(const ExternalReference& f)); |
| 381 explicit Operand(Handle<Object> handle); | 384 explicit Operand(Handle<Object> handle); |
| 382 INLINE(explicit Operand(Smi* value)); | 385 INLINE(explicit Operand(Smi* value)); |
| 383 | 386 |
| 384 // rm | 387 // rm |
| 385 INLINE(explicit Operand(Register rm)); | 388 INLINE(explicit Operand(Register rm)); |
| 386 | 389 |
| 387 // rm <shift_op> shift_imm | 390 // rm <shift_op> shift_imm |
| 388 explicit Operand(Register rm, ShiftOp shift_op, int shift_imm); | 391 explicit Operand(Register rm, ShiftOp shift_op, int shift_imm); |
| 389 | 392 |
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| 1412 public: | 1415 public: |
| 1413 explicit EnsureSpace(Assembler* assembler) { | 1416 explicit EnsureSpace(Assembler* assembler) { |
| 1414 assembler->CheckBuffer(); | 1417 assembler->CheckBuffer(); |
| 1415 } | 1418 } |
| 1416 }; | 1419 }; |
| 1417 | 1420 |
| 1418 | 1421 |
| 1419 } } // namespace v8::internal | 1422 } } // namespace v8::internal |
| 1420 | 1423 |
| 1421 #endif // V8_ARM_ASSEMBLER_ARM_H_ | 1424 #endif // V8_ARM_ASSEMBLER_ARM_H_ |
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