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Side by Side Diff: base/atomicops_internals_x86_gcc.h

Issue 7461141: Rename BASE_API to BASE_EXPORT. (Closed) Base URL: svn://svn.chromium.org/chrome/trunk/src/
Patch Set: '' Created 9 years, 4 months ago
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1 // Copyright (c) 2011 The Chromium Authors. All rights reserved. 1 // Copyright (c) 2011 The Chromium Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 // This file is an internal atomic implementation, use base/atomicops.h instead. 5 // This file is an internal atomic implementation, use base/atomicops.h instead.
6 6
7 #ifndef BASE_ATOMICOPS_INTERNALS_X86_GCC_H_ 7 #ifndef BASE_ATOMICOPS_INTERNALS_X86_GCC_H_
8 #define BASE_ATOMICOPS_INTERNALS_X86_GCC_H_ 8 #define BASE_ATOMICOPS_INTERNALS_X86_GCC_H_
9 #pragma once 9 #pragma once
10 10
11 #include "base/base_api.h" 11 #include "base/base_export.h"
12 12
13 // This struct is not part of the public API of this module; clients may not 13 // This struct is not part of the public API of this module; clients may not
14 // use it. (However, it's exported via BASE_API because clients implicitly 14 // use it. (However, it's exported via BASE_EXPORT because clients implicitly
15 // do use it at link time by inlining these functions.) 15 // do use it at link time by inlining these functions.)
16 // Features of this x86. Values may not be correct before main() is run, 16 // Features of this x86. Values may not be correct before main() is run,
17 // but are set conservatively. 17 // but are set conservatively.
18 struct AtomicOps_x86CPUFeatureStruct { 18 struct AtomicOps_x86CPUFeatureStruct {
19 bool has_amd_lock_mb_bug; // Processor has AMD memory-barrier bug; do lfence 19 bool has_amd_lock_mb_bug; // Processor has AMD memory-barrier bug; do lfence
20 // after acquire compare-and-swap. 20 // after acquire compare-and-swap.
21 bool has_sse2; // Processor has SSE2. 21 bool has_sse2; // Processor has SSE2.
22 }; 22 };
23 BASE_API extern struct AtomicOps_x86CPUFeatureStruct 23 BASE_EXPORT extern struct AtomicOps_x86CPUFeatureStruct
24 AtomicOps_Internalx86CPUFeatures; 24 AtomicOps_Internalx86CPUFeatures;
25 25
26 #define ATOMICOPS_COMPILER_BARRIER() __asm__ __volatile__("" : : : "memory") 26 #define ATOMICOPS_COMPILER_BARRIER() __asm__ __volatile__("" : : : "memory")
27 27
28 namespace base { 28 namespace base {
29 namespace subtle { 29 namespace subtle {
30 30
31 // 32-bit low-level operations on any platform. 31 // 32-bit low-level operations on any platform.
32 32
33 inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr, 33 inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
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261 } 261 }
262 262
263 #endif // defined(__x86_64__) 263 #endif // defined(__x86_64__)
264 264
265 } // namespace base::subtle 265 } // namespace base::subtle
266 } // namespace base 266 } // namespace base
267 267
268 #undef ATOMICOPS_COMPILER_BARRIER 268 #undef ATOMICOPS_COMPILER_BARRIER
269 269
270 #endif // BASE_ATOMICOPS_INTERNALS_X86_GCC_H_ 270 #endif // BASE_ATOMICOPS_INTERNALS_X86_GCC_H_
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