Revert 93066 - Execute all GL commands up to the put offset reported by a each flush.This means g...

content/common/gpu/gpu_channel.h

 // Copyright (c) 2011 The Chromium Authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef CONTENT_COMMON_GPU_GPU_CHANNEL_H_
 #define CONTENT_COMMON_GPU_GPU_CHANNEL_H_
 #pragma once
 
-#include <queue>
 #include <set>
 #include <string>
 #include <vector>
 
 #include "base/id_map.h"
 #include "base/memory/ref_counted.h"
 #include "base/memory/scoped_ptr.h"
 #include "base/process.h"
 #include "build/build_config.h"
 #include "gpu/command_buffer/service/surface_manager.h"
@@ skipping 52 matching lines @@
   }
 
   // IPC::Channel::Listener implementation:
   virtual bool OnMessageReceived(const IPC::Message& msg);
   virtual void OnChannelError();
   virtual void OnChannelConnected(int32 peer_pid);
 
   // IPC::Message::Sender implementation:
   virtual bool Send(IPC::Message* msg);
 
-  // Whether this channel is able to handle IPC messages.
-  bool IsScheduled();
-
-  // This is called when a command buffer transitions from the unscheduled
-  // state to the scheduled state, which potentially means the channel
-  // transitions from the unscheduled to the scheduled state. When this occurs
-  // deferred IPC messaged are handled.
-  void OnScheduled();
-
   void CreateViewCommandBuffer(
       gfx::PluginWindowHandle window,
       int32 render_view_id,
       const GPUCreateCommandBufferConfig& init_params,
       int32* route_id);
 
   void ViewResized(int32 command_buffer_route_id);
 
   gfx::GLShareGroup* share_group() const { return share_group_.get(); }
 
@@ skipping 33 matching lines @@
   // A callback which is called after a Set/WaitLatch command is processed.
   // The bool parameter will be true for SetLatch, and false for a WaitLatch
   // that is blocked. An unblocked WaitLatch will not trigger a callback.
   void OnLatchCallback(int route_id, bool is_set_latch);
 
  private:
   void OnDestroy();
 
   bool OnControlMessageReceived(const IPC::Message& msg);
 
-  void HandleDeferredMessages();
-
   int GenerateRouteID();
 
   // Message handlers.
   void OnInitialize(base::ProcessHandle renderer_process);
   void OnCreateOffscreenCommandBuffer(
       const gfx::Size& size,
       const GPUCreateCommandBufferConfig& init_params,
-      IPC::Message* reply_message);
-  void OnDestroyCommandBuffer(int32 route_id, IPC::Message* reply_message);
+      int32* route_id);
+  void OnDestroyCommandBuffer(int32 route_id);
 
   void OnCreateOffscreenSurface(const gfx::Size& size,
-                                IPC::Message* reply_message);
+                                int* route_id);
   void OnDestroySurface(int route_id);
 
   void OnCreateTransportTexture(int32 context_route_id, int32 host_id);
 
   // The lifetime of objects of this class is managed by a GpuChannelManager.
   // The GpuChannelManager destroy all the GpuChannels that they own when they
   // are destroyed. So a raw pointer is safe.
   GpuChannelManager* gpu_channel_manager_;
 
   scoped_ptr<IPC::SyncChannel> channel_;
 
-  std::queue<IPC::Message*> deferred_messages_;
-
   // The id of the renderer who is on the other side of the channel.
   int renderer_id_;
 
   // Handle to the renderer process that is on the other side of the channel.
   base::ProcessHandle renderer_process_;
 
   // The process id of the renderer process.
   base::ProcessId renderer_pid_;
 
   // Used to implement message routing functionality to CommandBuffer objects
@@ skipping 14 matching lines @@
 #endif  // defined (ENABLE_GPU)
 
   // A collection of transport textures created.
   typedef IDMap<TransportTexture, IDMapOwnPointer> TransportTextureMap;
   TransportTextureMap transport_textures_;
 
   bool log_messages_;  // True if we should log sent and received messages.
   gpu::gles2::DisallowedExtensions disallowed_extensions_;
   GpuWatchdog* watchdog_;
 
-  ScopedRunnableMethodFactory<GpuChannel> task_factory_;
-
   DISALLOW_COPY_AND_ASSIGN(GpuChannel);
 };
 
 #endif  // CONTENT_COMMON_GPU_GPU_CHANNEL_H_