Update the tcmalloc vendor branch to r111 (perftools version 1.8)

third_party/tcmalloc/vendor/src/base/atomicops.h

 /* Copyright (c) 2006, Google Inc.
  * All rights reserved.
  * 
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
  * met:
  * 
  *     * Redistributions of source code must retain the above copyright
  * notice, this list of conditions and the following disclaimer.
  *     * Redistributions in binary form must reproduce the above
@@ skipping 78 matching lines @@
 #include "base/arm_instruction_set_select.h"
 
 // TODO(csilvers): match piii, not just __i386.  Also, match k8
 #if defined(__MACH__) && defined(__APPLE__)
 #include "base/atomicops-internals-macosx.h"
 #elif defined(__GNUC__) && defined(ARMV6)
 #include "base/atomicops-internals-arm-v6plus.h"
 #elif defined(ARMV3)
 #include "base/atomicops-internals-arm-generic.h"
 #elif defined(_WIN32)
-#include "base/atomicops-internals-x86-windows.h"
+#include "base/atomicops-internals-windows.h"
 #elif defined(__GNUC__) && (defined(__i386) || defined(__x86_64__))
 #include "base/atomicops-internals-x86.h"
 #elif defined(__linux__) && defined(__PPC__)
 #include "base/atomicops-internals-linuxppc.h"
 #else
 // Assume x86 for now.  If you need to support a new architecture and
 // don't know how to implement atomic ops, you can probably get away
 // with using pthreads, since atomicops is only used by spinlock.h/cc
 //#error You need to implement atomic operations for this architecture
 #include "base/atomicops-internals-x86.h"
@@ skipping 272 matching lines @@
   return base::subtle::Acquire_Load(ptr);
 }
 inline base::subtle::Atomic64 Release_Load(
     volatile const base::subtle::Atomic64* ptr) {
   return base::subtle::Release_Load(ptr);
 }
 
 #endif  // BASE_HAS_ATOMIC64
 
 #endif  // THREAD_ATOMICOPS_H_