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Issue 7277084: Generate shorter instruction forms for constant in ia32 gap resolver. (Closed) Base URL: http://v8.googlecode.com/svn/branches/bleeding_edge/
Patch Set: Created 9 years, 5 months ago
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1 // Copyright 2011 the V8 project authors. All rights reserved. 1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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298 // moves. 298 // moves.
299 Register tmp = EnsureTempRegister(); 299 Register tmp = EnsureTempRegister();
300 Operand dst = cgen_->ToOperand(destination); 300 Operand dst = cgen_->ToOperand(destination);
301 __ mov(tmp, src); 301 __ mov(tmp, src);
302 __ mov(dst, tmp); 302 __ mov(dst, tmp);
303 } 303 }
304 304
305 } else if (source->IsConstantOperand()) { 305 } else if (source->IsConstantOperand()) {
306 ASSERT(destination->IsRegister() || destination->IsStackSlot()); 306 ASSERT(destination->IsRegister() || destination->IsStackSlot());
307 Immediate src = cgen_->ToImmediate(source); 307 Immediate src = cgen_->ToImmediate(source);
308 Operand dst = cgen_->ToOperand(destination); 308 if (destination->IsRegister()) {
309 __ mov(dst, src); 309 Register dst = cgen_->ToRegister(destination);
310 __ Set(dst, src);
311 } else {
312 Operand dst = cgen_->ToOperand(destination);
313 __ Set(dst, src);
314 }
310 315
311 } else if (source->IsDoubleRegister()) { 316 } else if (source->IsDoubleRegister()) {
312 XMMRegister src = cgen_->ToDoubleRegister(source); 317 XMMRegister src = cgen_->ToDoubleRegister(source);
313 if (destination->IsDoubleRegister()) { 318 if (destination->IsDoubleRegister()) {
314 XMMRegister dst = cgen_->ToDoubleRegister(destination); 319 XMMRegister dst = cgen_->ToDoubleRegister(destination);
315 __ movaps(dst, src); 320 __ movaps(dst, src);
316 } else { 321 } else {
317 ASSERT(destination->IsDoubleStackSlot()); 322 ASSERT(destination->IsDoubleStackSlot());
318 Operand dst = cgen_->ToOperand(destination); 323 Operand dst = cgen_->ToOperand(destination);
319 __ movdbl(dst, src); 324 __ movdbl(dst, src);
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466 } else if (destination->IsRegister()) { 471 } else if (destination->IsRegister()) {
467 source_uses_[destination->index()] = CountSourceUses(destination); 472 source_uses_[destination->index()] = CountSourceUses(destination);
468 } 473 }
469 } 474 }
470 475
471 #undef __ 476 #undef __
472 477
473 } } // namespace v8::internal 478 } } // namespace v8::internal
474 479
475 #endif // V8_TARGET_ARCH_IA32 480 #endif // V8_TARGET_ARCH_IA32
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