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Issue 7259010: MIPS: update missing write barrier for arguments store ICs, per comments. (Closed)
Patch Set: Created 9 years, 5 months ago
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1 // Copyright 2011 the V8 project authors. All rights reserved. 1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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999 // ---------- S t a t e -------------- 999 // ---------- S t a t e --------------
1000 // -- a0 : value 1000 // -- a0 : value
1001 // -- a1 : key 1001 // -- a1 : key
1002 // -- a2 : receiver 1002 // -- a2 : receiver
1003 // -- lr : return address 1003 // -- lr : return address
1004 // ----------------------------------- 1004 // -----------------------------------
1005 Label slow, notin; 1005 Label slow, notin;
1006 MemOperand mapped_location = 1006 MemOperand mapped_location =
1007 GenerateMappedArgumentsLookup(masm, a2, a1, a3, t0, t1, &notin, &slow); 1007 GenerateMappedArgumentsLookup(masm, a2, a1, a3, t0, t1, &notin, &slow);
1008 __ sw(a0, mapped_location); 1008 __ sw(a0, mapped_location);
1009 __ Addu(t2, a3, t1); 1009 // Verify mapped_location MemOperand is register, with no offset.
1010 __ RecordWrite(a3, t2, t5); 1010 ASSERT_EQ(mapped_location.offset(), 0);
1011 __ RecordWrite(a3, mapped_location.rm(), t5);
1011 __ Ret(USE_DELAY_SLOT); 1012 __ Ret(USE_DELAY_SLOT);
1012 __ mov(v0, a0); // (In delay slot) return the value stored in v0. 1013 __ mov(v0, a0); // (In delay slot) return the value stored in v0.
1013 __ bind(&notin); 1014 __ bind(&notin);
1014 // The unmapped lookup expects that the parameter map is in a3. 1015 // The unmapped lookup expects that the parameter map is in a3.
1015 MemOperand unmapped_location = 1016 MemOperand unmapped_location =
1016 GenerateUnmappedArgumentsLookup(masm, a1, a3, t0, &slow); 1017 GenerateUnmappedArgumentsLookup(masm, a1, a3, t0, &slow);
1017 __ sw(a0, unmapped_location); 1018 __ sw(a0, unmapped_location);
1018 __ Addu(t2, a3, t0); 1019 ASSERT_EQ(unmapped_location.offset(), 0);
1019 __ RecordWrite(a3, t2, t5); 1020 __ RecordWrite(a3, unmapped_location.rm(), t5);
1020 __ Ret(USE_DELAY_SLOT); 1021 __ Ret(USE_DELAY_SLOT);
1021 __ mov(v0, a0); // (In delay slot) return the value stored in v0. 1022 __ mov(v0, a0); // (In delay slot) return the value stored in v0.
1022 __ bind(&slow); 1023 __ bind(&slow);
1023 GenerateMiss(masm, false); 1024 GenerateMiss(masm, false);
1024 } 1025 }
1025 1026
1026 1027
1027 void KeyedCallIC::GenerateNonStrictArguments(MacroAssembler* masm, 1028 void KeyedCallIC::GenerateNonStrictArguments(MacroAssembler* masm,
1028 int argc) { 1029 int argc) {
1029 // ----------- S t a t e ------------- 1030 // ----------- S t a t e -------------
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1731 Register reg = Register::from_code(Assembler::GetRs(instr_at_patch)); 1732 Register reg = Register::from_code(Assembler::GetRs(instr_at_patch));
1732 patcher.masm()->andi(at, reg, kSmiTagMask); 1733 patcher.masm()->andi(at, reg, kSmiTagMask);
1733 patcher.ChangeBranchCondition(eq); 1734 patcher.ChangeBranchCondition(eq);
1734 } 1735 }
1735 } 1736 }
1736 1737
1737 1738
1738 } } // namespace v8::internal 1739 } } // namespace v8::internal
1739 1740
1740 #endif // V8_TARGET_ARCH_MIPS 1741 #endif // V8_TARGET_ARCH_MIPS
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