MIPS: port Add missing write barrier for arguments store ICs.

src/mips/ic-mips.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
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@@ skipping 988 matching lines @@
   // ---------- S t a t e --------------
   //  -- a0     : value
   //  -- a1     : key
   //  -- a2     : receiver
   //  -- lr     : return address
   // -----------------------------------
   Label slow, notin;
   MemOperand mapped_location =
       GenerateMappedArgumentsLookup(masm, a2, a1, a3, t0, t1, &notin, &slow);
   __ sw(a0, mapped_location);
+  __ Addu(t2, a3, t1);

[fschneider, 2011/06/24 09:13:38]

Since the store address is already computed by GenerateMappedArgumentsLookup
into t0, I think you could avoid this add here and just write:

__ RecordWrite(a3, t0, t5);

+  __ RecordWrite(a3, t2, t5);
   __ Ret(USE_DELAY_SLOT);
   __ mov(v0, a0);  // (In delay slot) return the value stored in v0.
   __ bind(&notin);
   // The unmapped lookup expects that the parameter map is in a3.
   MemOperand unmapped_location =
       GenerateUnmappedArgumentsLookup(masm, a1, a3, t0, &slow);
   __ sw(a0, unmapped_location);
+  __ Addu(t2, a3, t0);

[fschneider, 2011/06/24 09:13:38]

Same here. The store address is already computed into t0.

+  __ RecordWrite(a3, t2, t5);
   __ Ret(USE_DELAY_SLOT);
   __ mov(v0, a0);  // (In delay slot) return the value stored in v0.
   __ bind(&slow);
   GenerateMiss(masm, false);
 }
 
 
 void KeyedCallIC::GenerateNonStrictArguments(MacroAssembler* masm,
                                              int argc) {
   // ----------- S t a t e -------------
@@ skipping 701 matching lines @@
     Register reg = Register::from_code(Assembler::GetRs(instr_at_patch));
     patcher.masm()->andi(at, reg, kSmiTagMask);
     patcher.ChangeBranchCondition(eq);
   }
 }
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_MIPS