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Issue 7192006: Fix wrong parenthesis in stub ARM and MIPS generation code. (Closed) Base URL: http://v8.googlecode.com/svn/branches/bleeding_edge/
Patch Set: Created 9 years, 6 months ago
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1 // Copyright 2011 the V8 project authors. All rights reserved. 1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
(...skipping 2672 matching lines...) Expand 10 before | Expand all | Expand 10 after
2683 GenerateSmiSmiOperation(masm); 2683 GenerateSmiSmiOperation(masm);
2684 // Fall through if the result is not a smi. 2684 // Fall through if the result is not a smi.
2685 __ bind(&skip); 2685 __ bind(&skip);
2686 2686
2687 switch (op_) { 2687 switch (op_) {
2688 case Token::ADD: 2688 case Token::ADD:
2689 case Token::SUB: 2689 case Token::SUB:
2690 case Token::MUL: 2690 case Token::MUL:
2691 case Token::DIV: 2691 case Token::DIV:
2692 case Token::MOD: { 2692 case Token::MOD: {
2693 // Load both operands and check that they are 32-bit integer. 2693 // Load both operands and check that they are 32-bit integer.
2694 // Jump to type transition if they are not. The registers a0 and a1 (right 2694 // Jump to type transition if they are not. The registers a0 and a1 (right
2695 // and left) are preserved for the runtime call. 2695 // and left) are preserved for the runtime call.
2696 FloatingPointHelper::Destination destination = 2696 FloatingPointHelper::Destination destination =
2697 CpuFeatures::IsSupported(FPU) && 2697 (CpuFeatures::IsSupported(FPU) && op_ != Token::MOD)
2698 op_ != Token::MOD ? 2698 ? FloatingPointHelper::kFPURegisters
2699 FloatingPointHelper::kFPURegisters : 2699 : FloatingPointHelper::kCoreRegisters;
2700 FloatingPointHelper::kCoreRegisters;
2701 2700
2702 FloatingPointHelper::LoadNumberAsInt32Double(masm, 2701 FloatingPointHelper::LoadNumberAsInt32Double(masm,
2703 right, 2702 right,
2704 destination, 2703 destination,
2705 f14, 2704 f14,
2706 a2, 2705 a2,
2707 a3, 2706 a3,
2708 heap_number_map, 2707 heap_number_map,
2709 scratch1, 2708 scratch1,
2710 scratch2, 2709 scratch2,
2711 f2, 2710 f2,
2712 &transition); 2711 &transition);
2713 FloatingPointHelper::LoadNumberAsInt32Double(masm, 2712 FloatingPointHelper::LoadNumberAsInt32Double(masm,
2714 left, 2713 left,
2715 destination, 2714 destination,
2716 f12, 2715 f12,
2717 t0, 2716 t0,
2718 t1, 2717 t1,
2719 heap_number_map, 2718 heap_number_map,
2720 scratch1, 2719 scratch1,
2721 scratch2, 2720 scratch2,
2722 f2, 2721 f2,
2723 &transition); 2722 &transition);
2724 2723
2725 if (destination == FloatingPointHelper::kFPURegisters) { 2724 if (destination == FloatingPointHelper::kFPURegisters) {
2726 CpuFeatures::Scope scope(FPU); 2725 CpuFeatures::Scope scope(FPU);
2727 Label return_heap_number; 2726 Label return_heap_number;
2728 switch (op_) { 2727 switch (op_) {
2729 case Token::ADD: 2728 case Token::ADD:
2730 __ add_d(f10, f12, f14); 2729 __ add_d(f10, f12, f14);
2731 break; 2730 break;
2732 case Token::SUB: 2731 case Token::SUB:
2733 __ sub_d(f10, f12, f14); 2732 __ sub_d(f10, f12, f14);
(...skipping 49 matching lines...) Expand 10 before | Expand all | Expand 10 after
2783 __ Branch(&return_heap_number, ne, scratch2, Operand(zero_reg)); 2782 __ Branch(&return_heap_number, ne, scratch2, Operand(zero_reg));
2784 __ bind(&not_zero); 2783 __ bind(&not_zero);
2785 2784
2786 // Tag the result and return. 2785 // Tag the result and return.
2787 __ SmiTag(v0, scratch1); 2786 __ SmiTag(v0, scratch1);
2788 __ Ret(); 2787 __ Ret();
2789 } else { 2788 } else {
2790 // DIV just falls through to allocating a heap number. 2789 // DIV just falls through to allocating a heap number.
2791 } 2790 }
2792 2791
2793 if (result_type_ >= (op_ == Token::DIV) ? BinaryOpIC::HEAP_NUMBER 2792 if (result_type_ >= ((op_ == Token::DIV) ? BinaryOpIC::HEAP_NUMBER
2794 : BinaryOpIC::INT32) { 2793 : BinaryOpIC::INT32)) {
2795 __ bind(&return_heap_number); 2794 __ bind(&return_heap_number);
2796 // We are using FPU registers so s0 is available. 2795 // We are using FPU registers so s0 is available.
2797 heap_number_result = s0; 2796 heap_number_result = s0;
2798 GenerateHeapResultAllocation(masm, 2797 GenerateHeapResultAllocation(masm,
2799 heap_number_result, 2798 heap_number_result,
2800 heap_number_map, 2799 heap_number_map,
2801 scratch1, 2800 scratch1,
2802 scratch2, 2801 scratch2,
2803 &call_runtime); 2802 &call_runtime);
2804 __ mov(v0, heap_number_result); 2803 __ mov(v0, heap_number_result);
(...skipping 3850 matching lines...) Expand 10 before | Expand all | Expand 10 after
6655 __ mov(result, zero_reg); 6654 __ mov(result, zero_reg);
6656 __ Ret(); 6655 __ Ret();
6657 } 6656 }
6658 6657
6659 6658
6660 #undef __ 6659 #undef __
6661 6660
6662 } } // namespace v8::internal 6661 } } // namespace v8::internal
6663 6662
6664 #endif // V8_TARGET_ARCH_MIPS 6663 #endif // V8_TARGET_ARCH_MIPS
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