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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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160 *m = code_ & 0x1; | 160 *m = code_ & 0x1; |
161 *vm = code_ >> 1; | 161 *vm = code_ >> 1; |
162 } | 162 } |
163 | 163 |
164 int code_; | 164 int code_; |
165 }; | 165 }; |
166 | 166 |
167 | 167 |
168 // Double word VFP register. | 168 // Double word VFP register. |
169 struct DwVfpRegister { | 169 struct DwVfpRegister { |
170 // d0 has been excluded from allocation. This is following ia32 | |
171 // where xmm0 is excluded. This should be revisited. | |
172 // Currently d0 is used as a scratch register. | |
173 // d1 has also been excluded from allocation to be used as a scratch | |
174 // register as well. | |
175 static const int kNumRegisters = 16; | 170 static const int kNumRegisters = 16; |
176 static const int kNumAllocatableRegisters = 15; | 171 // A few double registers are reserved: one as a scratch register and one to |
| 172 // hold 0.0, that does not fit in the immediate field of vmov instructions. |
| 173 // d14: 0.0 |
| 174 // d15: scratch register. |
| 175 static const int kNumReservedRegisters = 2; |
| 176 static const int kNumAllocatableRegisters = kNumRegisters - |
| 177 kNumReservedRegisters; |
177 | 178 |
178 static int ToAllocationIndex(DwVfpRegister reg) { | 179 static int ToAllocationIndex(DwVfpRegister reg) { |
179 ASSERT(reg.code() != 0); | 180 ASSERT(reg.code() != 0); |
180 return reg.code() - 1; | 181 return reg.code() - 1; |
181 } | 182 } |
182 | 183 |
183 static DwVfpRegister FromAllocationIndex(int index) { | 184 static DwVfpRegister FromAllocationIndex(int index) { |
184 ASSERT(index >= 0 && index < kNumAllocatableRegisters); | 185 ASSERT(index >= 0 && index < kNumAllocatableRegisters); |
185 return from_code(index + 1); | 186 return from_code(index + 1); |
186 } | 187 } |
187 | 188 |
188 static const char* AllocationIndexToString(int index) { | 189 static const char* AllocationIndexToString(int index) { |
189 ASSERT(index >= 0 && index < kNumAllocatableRegisters); | 190 ASSERT(index >= 0 && index < kNumAllocatableRegisters); |
190 const char* const names[] = { | 191 const char* const names[] = { |
| 192 "d0", |
191 "d1", | 193 "d1", |
192 "d2", | 194 "d2", |
193 "d3", | 195 "d3", |
194 "d4", | 196 "d4", |
195 "d5", | 197 "d5", |
196 "d6", | 198 "d6", |
197 "d7", | 199 "d7", |
198 "d8", | 200 "d8", |
199 "d9", | 201 "d9", |
200 "d10", | 202 "d10", |
201 "d11", | 203 "d11", |
202 "d12", | 204 "d12", |
203 "d13", | 205 "d13" |
204 "d14", | |
205 "d15" | |
206 }; | 206 }; |
207 return names[index]; | 207 return names[index]; |
208 } | 208 } |
209 | 209 |
210 static DwVfpRegister from_code(int code) { | 210 static DwVfpRegister from_code(int code) { |
211 DwVfpRegister r = { code }; | 211 DwVfpRegister r = { code }; |
212 return r; | 212 return r; |
213 } | 213 } |
214 | 214 |
215 // Supporting d0 to d15, can be later extended to d31. | 215 // Supporting d0 to d15, can be later extended to d31. |
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299 const DwVfpRegister d10 = { 10 }; | 299 const DwVfpRegister d10 = { 10 }; |
300 const DwVfpRegister d11 = { 11 }; | 300 const DwVfpRegister d11 = { 11 }; |
301 const DwVfpRegister d12 = { 12 }; | 301 const DwVfpRegister d12 = { 12 }; |
302 const DwVfpRegister d13 = { 13 }; | 302 const DwVfpRegister d13 = { 13 }; |
303 const DwVfpRegister d14 = { 14 }; | 303 const DwVfpRegister d14 = { 14 }; |
304 const DwVfpRegister d15 = { 15 }; | 304 const DwVfpRegister d15 = { 15 }; |
305 | 305 |
306 // Aliases for double registers. | 306 // Aliases for double registers. |
307 const DwVfpRegister kFirstCalleeSavedDoubleReg = d8; | 307 const DwVfpRegister kFirstCalleeSavedDoubleReg = d8; |
308 const DwVfpRegister kLastCalleeSavedDoubleReg = d15; | 308 const DwVfpRegister kLastCalleeSavedDoubleReg = d15; |
| 309 const DwVfpRegister kDoubleRegZero = d14; |
309 | 310 |
310 | 311 |
311 // Coprocessor register | 312 // Coprocessor register |
312 struct CRegister { | 313 struct CRegister { |
313 bool is_valid() const { return 0 <= code_ && code_ < 16; } | 314 bool is_valid() const { return 0 <= code_ && code_ < 16; } |
314 bool is(CRegister creg) const { return code_ == creg.code_; } | 315 bool is(CRegister creg) const { return code_ == creg.code_; } |
315 int code() const { | 316 int code() const { |
316 ASSERT(is_valid()); | 317 ASSERT(is_valid()); |
317 return code_; | 318 return code_; |
318 } | 319 } |
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1396 public: | 1397 public: |
1397 explicit EnsureSpace(Assembler* assembler) { | 1398 explicit EnsureSpace(Assembler* assembler) { |
1398 assembler->CheckBuffer(); | 1399 assembler->CheckBuffer(); |
1399 } | 1400 } |
1400 }; | 1401 }; |
1401 | 1402 |
1402 | 1403 |
1403 } } // namespace v8::internal | 1404 } } // namespace v8::internal |
1404 | 1405 |
1405 #endif // V8_ARM_ASSEMBLER_ARM_H_ | 1406 #endif // V8_ARM_ASSEMBLER_ARM_H_ |
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