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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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160 *m = code_ & 0x1; | 160 *m = code_ & 0x1; |
161 *vm = code_ >> 1; | 161 *vm = code_ >> 1; |
162 } | 162 } |
163 | 163 |
164 int code_; | 164 int code_; |
165 }; | 165 }; |
166 | 166 |
167 | 167 |
168 // Double word VFP register. | 168 // Double word VFP register. |
169 struct DwVfpRegister { | 169 struct DwVfpRegister { |
170 // d0 has been excluded from allocation. This is following ia32 | |
171 // where xmm0 is excluded. This should be revisited. | |
172 // Currently d0 is used as a scratch register. | |
173 // d1 has also been excluded from allocation to be used as a scratch | |
174 // register as well. | |
175 static const int kNumRegisters = 16; | 170 static const int kNumRegisters = 16; |
176 static const int kNumAllocatableRegisters = 15; | 171 // A few double registers are reserved: one as a scratch register and three |
172 // for common values not fitting the immediate field of vmov instructions. | |
Søren Thygesen Gjesse
2011/06/16 09:38:07
It seems to be some of a waste to use 3 double reg
Alexandre
2011/06/16 12:58:48
I thought we never put enough pressure on double r
| |
173 // d12: 255.0 | |
174 // d13: -0.0 | |
175 // d14: 0.0 | |
176 // d15: scratch register. | |
177 static const int kNumReservedRegisters = 4; | |
178 static const int kNumAllocatableRegisters = kNumRegisters - | |
179 kNumReservedRegisters; | |
177 | 180 |
178 static int ToAllocationIndex(DwVfpRegister reg) { | 181 static int ToAllocationIndex(DwVfpRegister reg) { |
179 ASSERT(reg.code() != 0); | 182 ASSERT(reg.code() != 0); |
180 return reg.code() - 1; | 183 return reg.code() - 1; |
181 } | 184 } |
182 | 185 |
183 static DwVfpRegister FromAllocationIndex(int index) { | 186 static DwVfpRegister FromAllocationIndex(int index) { |
184 ASSERT(index >= 0 && index < kNumAllocatableRegisters); | 187 ASSERT(index >= 0 && index < kNumAllocatableRegisters); |
185 return from_code(index + 1); | 188 return from_code(index + 1); |
186 } | 189 } |
187 | 190 |
188 static const char* AllocationIndexToString(int index) { | 191 static const char* AllocationIndexToString(int index) { |
189 ASSERT(index >= 0 && index < kNumAllocatableRegisters); | 192 ASSERT(index >= 0 && index < kNumAllocatableRegisters); |
190 const char* const names[] = { | 193 const char* const names[] = { |
194 "d0", | |
191 "d1", | 195 "d1", |
192 "d2", | 196 "d2", |
193 "d3", | 197 "d3", |
194 "d4", | 198 "d4", |
195 "d5", | 199 "d5", |
196 "d6", | 200 "d6", |
197 "d7", | 201 "d7", |
198 "d8", | 202 "d8", |
199 "d9", | 203 "d9", |
200 "d10", | 204 "d10", |
201 "d11", | 205 "d11" |
202 "d12", | |
203 "d13", | |
204 "d14", | |
205 "d15" | |
206 }; | 206 }; |
207 return names[index]; | 207 return names[index]; |
208 } | 208 } |
209 | 209 |
210 static DwVfpRegister from_code(int code) { | 210 static DwVfpRegister from_code(int code) { |
211 DwVfpRegister r = { code }; | 211 DwVfpRegister r = { code }; |
212 return r; | 212 return r; |
213 } | 213 } |
214 | 214 |
215 // Supporting d0 to d15, can be later extended to d31. | 215 // Supporting d0 to d15, can be later extended to d31. |
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296 const DwVfpRegister d7 = { 7 }; | 296 const DwVfpRegister d7 = { 7 }; |
297 const DwVfpRegister d8 = { 8 }; | 297 const DwVfpRegister d8 = { 8 }; |
298 const DwVfpRegister d9 = { 9 }; | 298 const DwVfpRegister d9 = { 9 }; |
299 const DwVfpRegister d10 = { 10 }; | 299 const DwVfpRegister d10 = { 10 }; |
300 const DwVfpRegister d11 = { 11 }; | 300 const DwVfpRegister d11 = { 11 }; |
301 const DwVfpRegister d12 = { 12 }; | 301 const DwVfpRegister d12 = { 12 }; |
302 const DwVfpRegister d13 = { 13 }; | 302 const DwVfpRegister d13 = { 13 }; |
303 const DwVfpRegister d14 = { 14 }; | 303 const DwVfpRegister d14 = { 14 }; |
304 const DwVfpRegister d15 = { 15 }; | 304 const DwVfpRegister d15 = { 15 }; |
305 | 305 |
306 // Aliases for double registers. | |
307 const DwVfpRegister kFirstCalleeSavedDoubleReg = d8; | |
308 const DwVfpRegister kLastCalleeSavedDoubleReg = d15; | |
309 const DwVfpRegister kDoubleReg255 = d12; | |
310 const DwVfpRegister kDoubleRegMinusZero = d13; | |
311 const DwVfpRegister kDoubleRegZero = d14; | |
312 | |
306 | 313 |
307 // Coprocessor register | 314 // Coprocessor register |
308 struct CRegister { | 315 struct CRegister { |
309 bool is_valid() const { return 0 <= code_ && code_ < 16; } | 316 bool is_valid() const { return 0 <= code_ && code_ < 16; } |
310 bool is(CRegister creg) const { return code_ == creg.code_; } | 317 bool is(CRegister creg) const { return code_ == creg.code_; } |
311 int code() const { | 318 int code() const { |
312 ASSERT(is_valid()); | 319 ASSERT(is_valid()); |
313 return code_; | 320 return code_; |
314 } | 321 } |
315 int bit() const { | 322 int bit() const { |
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1369 public: | 1376 public: |
1370 explicit EnsureSpace(Assembler* assembler) { | 1377 explicit EnsureSpace(Assembler* assembler) { |
1371 assembler->CheckBuffer(); | 1378 assembler->CheckBuffer(); |
1372 } | 1379 } |
1373 }; | 1380 }; |
1374 | 1381 |
1375 | 1382 |
1376 } } // namespace v8::internal | 1383 } } // namespace v8::internal |
1377 | 1384 |
1378 #endif // V8_ARM_ASSEMBLER_ARM_H_ | 1385 #endif // V8_ARM_ASSEMBLER_ARM_H_ |
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