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1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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323 Condition cond) { | 323 Condition cond) { |
324 if (!src2.is_reg() && | 324 if (!src2.is_reg() && |
325 !src2.must_use_constant_pool() && | 325 !src2.must_use_constant_pool() && |
326 src2.immediate() == 0) { | 326 src2.immediate() == 0) { |
327 mov(dst, Operand(0, RelocInfo::NONE), LeaveCC, cond); | 327 mov(dst, Operand(0, RelocInfo::NONE), LeaveCC, cond); |
328 | 328 |
329 } else if (!src2.is_single_instruction() && | 329 } else if (!src2.is_single_instruction() && |
330 !src2.must_use_constant_pool() && | 330 !src2.must_use_constant_pool() && |
331 CpuFeatures::IsSupported(ARMv7) && | 331 CpuFeatures::IsSupported(ARMv7) && |
332 IsPowerOf2(src2.immediate() + 1)) { | 332 IsPowerOf2(src2.immediate() + 1)) { |
333 ubfx(dst, src1, 0, WhichPowerOf2(src2.immediate() + 1), cond); | 333 ubfx(dst, src1, 0, |
| 334 WhichPowerOf2(static_cast<uint32_t>(src2.immediate()) + 1), cond); |
334 | 335 |
335 } else { | 336 } else { |
336 and_(dst, src1, src2, LeaveCC, cond); | 337 and_(dst, src1, src2, LeaveCC, cond); |
337 } | 338 } |
338 } | 339 } |
339 | 340 |
340 | 341 |
341 void MacroAssembler::Ubfx(Register dst, Register src1, int lsb, int width, | 342 void MacroAssembler::Ubfx(Register dst, Register src1, int lsb, int width, |
342 Condition cond) { | 343 Condition cond) { |
343 ASSERT(lsb < 32); | 344 ASSERT(lsb < 32); |
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3157 void CodePatcher::EmitCondition(Condition cond) { | 3158 void CodePatcher::EmitCondition(Condition cond) { |
3158 Instr instr = Assembler::instr_at(masm_.pc_); | 3159 Instr instr = Assembler::instr_at(masm_.pc_); |
3159 instr = (instr & ~kCondMask) | cond; | 3160 instr = (instr & ~kCondMask) | cond; |
3160 masm_.emit(instr); | 3161 masm_.emit(instr); |
3161 } | 3162 } |
3162 | 3163 |
3163 | 3164 |
3164 } } // namespace v8::internal | 3165 } } // namespace v8::internal |
3165 | 3166 |
3166 #endif // V8_TARGET_ARCH_ARM | 3167 #endif // V8_TARGET_ARCH_ARM |
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