Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(348)

Side by Side Diff: src/mips/constants-mips.h

Issue 6993054: MIPS: Fixed FPU rounding checks and related errors in the Simulator. (Closed)
Patch Set: Created 9 years, 6 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
« no previous file with comments | « src/mips/code-stubs-mips.cc ('k') | src/mips/macro-assembler-mips.cc » ('j') | no next file with comments »
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
1 // Copyright 2010 the V8 project authors. All rights reserved. 1 // Copyright 2010 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
(...skipping 75 matching lines...) Expand 10 before | Expand all | Expand 10 after
86 // Number coprocessor registers. 86 // Number coprocessor registers.
87 static const int kNumFPURegisters = 32; 87 static const int kNumFPURegisters = 32;
88 static const int kInvalidFPURegister = -1; 88 static const int kInvalidFPURegister = -1;
89 89
90 // FPU (coprocessor 1) control registers. Currently only FCSR is implemented. 90 // FPU (coprocessor 1) control registers. Currently only FCSR is implemented.
91 static const int kFCSRRegister = 31; 91 static const int kFCSRRegister = 31;
92 static const int kInvalidFPUControlRegister = -1; 92 static const int kInvalidFPUControlRegister = -1;
93 static const uint32_t kFPUInvalidResult = (uint32_t) (1 << 31) - 1; 93 static const uint32_t kFPUInvalidResult = (uint32_t) (1 << 31) - 1;
94 94
95 // FCSR constants. 95 // FCSR constants.
96 static const uint32_t kFCSRFlagMask = (1 << 6) - 1; 96 static const uint32_t kFCSRInexactFlagBit = 2;
97 static const uint32_t kFCSRFlagShift = 2; 97 static const uint32_t kFCSRUnderflowFlagBit = 3;
98 static const uint32_t kFCSRInexactFlagBit = 1 << 0; 98 static const uint32_t kFCSROverflowFlagBit = 4;
99 static const uint32_t kFCSRUnderflowFlagBit = 1 << 1; 99 static const uint32_t kFCSRDivideByZeroFlagBit = 5;
100 static const uint32_t kFCSROverflowFlagBit = 1 << 2; 100 static const uint32_t kFCSRInvalidOpFlagBit = 6;
101 static const uint32_t kFCSRDivideByZeroFlagBit = 1 << 3; 101
102 static const uint32_t kFCSRInvalidOpFlagBit = 1 << 4; 102 static const uint32_t kFCSRInexactFlagMask = 1 << kFCSRInexactFlagBit;
103 static const uint32_t kFCSRUnderflowFlagMask = 1 << kFCSRUnderflowFlagBit;
104 static const uint32_t kFCSROverflowFlagMask = 1 << kFCSROverflowFlagBit;
105 static const uint32_t kFCSRDivideByZeroFlagMask = 1 << kFCSRDivideByZeroFlagBit;
106 static const uint32_t kFCSRInvalidOpFlagMask = 1 << kFCSRInvalidOpFlagBit;
107
108 static const uint32_t kFCSRFlagMask = kFCSRInexactFlagMask |
109 kFCSRUnderflowFlagMask |
Mads Ager (chromium) 2011/06/06 08:39:02 Four-space indent for these.
110 kFCSROverflowFlagMask |
111 kFCSRDivideByZeroFlagMask |
112 kFCSRInvalidOpFlagMask;
113
114 static const uint32_t kFCSRExceptionFlagMask = kFCSRFlagMask ^
115 kFCSRInexactFlagMask;
Mads Ager (chromium) 2011/06/06 08:39:02 Four-space indent.
103 116
104 // Helper functions for converting between register numbers and names. 117 // Helper functions for converting between register numbers and names.
105 class Registers { 118 class Registers {
106 public: 119 public:
107 // Return the name of the register. 120 // Return the name of the register.
108 static const char* Name(int reg); 121 static const char* Name(int reg);
109 122
110 // Lookup the register number for the name provided. 123 // Lookup the register number for the name provided.
111 static int Number(const char* name); 124 static int Number(const char* name);
112 125
(...skipping 629 matching lines...) Expand 10 before | Expand all | Expand 10 after
742 755
743 static const int kDoubleAlignmentBits = 3; 756 static const int kDoubleAlignmentBits = 3;
744 static const int kDoubleAlignment = (1 << kDoubleAlignmentBits); 757 static const int kDoubleAlignment = (1 << kDoubleAlignmentBits);
745 static const int kDoubleAlignmentMask = kDoubleAlignment - 1; 758 static const int kDoubleAlignmentMask = kDoubleAlignment - 1;
746 759
747 760
748 } } // namespace v8::internal 761 } } // namespace v8::internal
749 762
750 #endif // #ifndef V8_MIPS_CONSTANTS_H_ 763 #endif // #ifndef V8_MIPS_CONSTANTS_H_
751 764
OLDNEW
« no previous file with comments | « src/mips/code-stubs-mips.cc ('k') | src/mips/macro-assembler-mips.cc » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698