Update mips infrastructure files.

test/cctest/test-assembler-mips.cc

-// Copyright 2010 the V8 project authors. All rights reserved.
+// Copyright 2011 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
 //       with the distribution.
@@ skipping 45 matching lines @@
 }
 
 
 #define __ assm.
 
 
 TEST(MIPS0) {
   InitializeVM();
   v8::HandleScope scope;
 
-  MacroAssembler assm(NULL, 0);
+  MacroAssembler assm(Isolate::Current(), NULL, 0);
 
   // Addition.
   __ addu(v0, a0, a1);
   __ jr(ra);
   __ nop();
 
   CodeDesc desc;
   assm.GetCode(&desc);
   Object* code = HEAP->CreateCode(
       desc,
       Code::ComputeFlags(Code::STUB),
       Handle<Object>(HEAP->undefined_value()))->ToObjectChecked();
   CHECK(code->IsCode());
   F2 f = FUNCTION_CAST<F2>(Code::cast(code)->entry());
   int res = reinterpret_cast<int>(CALL_GENERATED_CODE(f, 0xab0, 0xc, 0, 0, 0));
   ::printf("f() = %d\n", res);
   CHECK_EQ(0xabc, res);
 }
 
 
 TEST(MIPS1) {
   InitializeVM();
   v8::HandleScope scope;
 
-  MacroAssembler assm(NULL, 0);
+  MacroAssembler assm(Isolate::Current(), NULL, 0);
   Label L, C;
 
   __ mov(a1, a0);
   __ li(v0, 0);
   __ b(&C);
   __ nop();
 
   __ bind(&L);
   __ addu(v0, v0, a1);
   __ addiu(a1, a1, -1);
@@ skipping 17 matching lines @@
   int res = reinterpret_cast<int>(CALL_GENERATED_CODE(f, 50, 0, 0, 0, 0));
   ::printf("f() = %d\n", res);
   CHECK_EQ(1275, res);
 }
 
 
 TEST(MIPS2) {
   InitializeVM();
   v8::HandleScope scope;
 
-  MacroAssembler assm(NULL, 0);
+  MacroAssembler assm(Isolate::Current(), NULL, 0);
 
   Label exit, error;
 
   // ----- Test all instructions.
 
   // Test lui, ori, and addiu, used in the li pseudo-instruction.
   // This way we can then safely load registers with chosen values.
 
   __ ori(t0, zero_reg, 0);
   __ lui(t0, 0x1234);
@@ skipping 133 matching lines @@
     double c;
     double d;
     double e;
     double f;
     double g;
   } T;
   T t;
 
   // Create a function that accepts &t, and loads, manipulates, and stores
   // the doubles t.a ... t.f.
-  MacroAssembler assm(NULL, 0);
+  MacroAssembler assm(Isolate::Current(), NULL, 0);
   Label L, C;
 
-  if (Isolate::Current()->cpu_features()->IsSupported(FPU)) {
+  if (CpuFeatures::IsSupported(FPU)) {
     CpuFeatures::Scope scope(FPU);
 
     __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
     __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) );
     __ add_d(f8, f4, f6);
     __ sdc1(f8, MemOperand(a0, OFFSET_OF(T, c)) );  // c = a + b.
 
     __ mov_d(f10, f8);  // c
     __ neg_d(f12, f6);  // -b
     __ sub_d(f10, f10, f12);
@@ skipping 49 matching lines @@
   InitializeVM();
   v8::HandleScope scope;
 
   typedef struct {
     double a;
     double b;
     double c;
   } T;
   T t;
 
-  Assembler assm(NULL, 0);
+  Assembler assm(Isolate::Current(), NULL, 0);
   Label L, C;
 
-  if (Isolate::Current()->cpu_features()->IsSupported(FPU)) {
+  if (CpuFeatures::IsSupported(FPU)) {
     CpuFeatures::Scope scope(FPU);
 
     __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
     __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) );
 
     // Swap f4 and f6, by using four integer registers, t0-t3.
     __ mfc1(t0, f4);
     __ mfc1(t1, f5);
     __ mfc1(t2, f6);
     __ mfc1(t3, f7);
@@ skipping 37 matching lines @@
   v8::HandleScope scope;
 
   typedef struct {
     double a;
     double b;
     int i;
     int j;
   } T;
   T t;
 
-  Assembler assm(NULL, 0);
+  Assembler assm(Isolate::Current(), NULL, 0);
   Label L, C;
 
-  if (Isolate::Current()->cpu_features()->IsSupported(FPU)) {
+  if (CpuFeatures::IsSupported(FPU)) {
     CpuFeatures::Scope scope(FPU);
 
     // Load all structure elements to registers.
     __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
     __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) );
     __ lw(t0, MemOperand(a0, OFFSET_OF(T, i)) );
     __ lw(t1, MemOperand(a0, OFFSET_OF(T, j)) );
 
     // Convert double in f4 to int in element i.
     __ cvt_w_d(f8, f4);
@@ skipping 51 matching lines @@
     int32_t si;
     int32_t r1;
     int32_t r2;
     int32_t r3;
     int32_t r4;
     int32_t r5;
     int32_t r6;
   } T;
   T t;
 
-  Assembler assm(NULL, 0);
+  Assembler assm(Isolate::Current(), NULL, 0);
   Label L, C;
 
   // Basic word load/store.
   __ lw(t0, MemOperand(a0, OFFSET_OF(T, ui)) );
   __ sw(t0, MemOperand(a0, OFFSET_OF(T, r1)) );
 
   // lh with positive data.
   __ lh(t1, MemOperand(a0, OFFSET_OF(T, ui)) );
   __ sw(t1, MemOperand(a0, OFFSET_OF(T, r2)) );
 
@@ skipping 52 matching lines @@
     double c;
     double d;
     double e;
     double f;
     int32_t result;
   } T;
   T t;
 
   // Create a function that accepts &t, and loads, manipulates, and stores
   // the doubles t.a ... t.f.
-  MacroAssembler assm(NULL, 0);
+  MacroAssembler assm(Isolate::Current(), NULL, 0);
   Label neither_is_nan, less_than, outa_here;
 
-  if (Isolate::Current()->cpu_features()->IsSupported(FPU)) {
+  if (CpuFeatures::IsSupported(FPU)) {
     CpuFeatures::Scope scope(FPU);
 
     __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
     __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) );
     __ c(UN, D, f4, f6);
     __ bc1f(&neither_is_nan);
     __ nop();
     __ sw(zero_reg, MemOperand(a0, OFFSET_OF(T, result)) );
     __ Branch(&outa_here);
 
@@ skipping 58 matching lines @@
     int32_t result_rotrv_4;
     int32_t result_rotrv_8;
     int32_t result_rotrv_12;
     int32_t result_rotrv_16;
     int32_t result_rotrv_20;
     int32_t result_rotrv_24;
     int32_t result_rotrv_28;
   } T;
   T t;
 
-  MacroAssembler assm(NULL, 0);
+  MacroAssembler assm(Isolate::Current(), NULL, 0);
 
   // Basic word load.
   __ lw(t0, MemOperand(a0, OFFSET_OF(T, input)) );
 
   // ROTR instruction (called through the Ror macro).
   __ Ror(t1, t0, 0x0004);
   __ Ror(t2, t0, 0x0008);
   __ Ror(t3, t0, 0x000c);
   __ Ror(t4, t0, 0x0010);
   __ Ror(t5, t0, 0x0014);
@@ skipping 64 matching lines @@
   CHECK_EQ(0x34567812, t.result_rotrv_24);
   CHECK_EQ(0x23456781, t.result_rotrv_28);
 }
 
 
 TEST(MIPS9) {
   // Test BRANCH improvements.
   InitializeVM();
   v8::HandleScope scope;
 
-  MacroAssembler assm(NULL, 0);
+  MacroAssembler assm(Isolate::Current(), NULL, 0);
   Label exit, exit2, exit3;
 
   __ Branch(&exit, ge, a0, Operand(0x00000000));
   __ Branch(&exit2, ge, a0, Operand(0x00001FFF));
   __ Branch(&exit3, ge, a0, Operand(0x0001FFFF));
 
   __ bind(&exit);
   __ bind(&exit2);
   __ bind(&exit3);
   __ jr(ra);
@@ skipping 20 matching lines @@
     double b;
     int32_t dbl_mant;
     int32_t dbl_exp;
     int32_t long_hi;
     int32_t long_lo;
     int32_t b_long_hi;
     int32_t b_long_lo;
   } T;
   T t;
 
-  Assembler assm(NULL, 0);
+  Assembler assm(Isolate::Current(), NULL, 0);
   Label L, C;
 
-  if (Isolate::Current()->cpu_features()->IsSupported(FPU)) {
+  if (CpuFeatures::IsSupported(FPU)) {
     CpuFeatures::Scope scope(FPU);
 
     // Load all structure elements to registers.
     __ ldc1(f0, MemOperand(a0, OFFSET_OF(T, a)));
 
     // Save the raw bits of the double.
     __ mfc1(t0, f0);
     __ mfc1(t1, f1);
     __ sw(t0, MemOperand(a0, OFFSET_OF(T, dbl_mant)));
     __ sw(t1, MemOperand(a0, OFFSET_OF(T, dbl_exp)));
@@ skipping 60 matching lines @@
     int32_t swl_1;
     int32_t swl_2;
     int32_t swl_3;
     int32_t swr_0;
     int32_t swr_1;
     int32_t swr_2;
     int32_t swr_3;
   } T;
   T t;
 
-  Assembler assm(NULL, 0);
+  Assembler assm(Isolate::Current(), NULL, 0);
 
   // Test all combinations of LWL and vAddr.
   __ lw(t0, MemOperand(a0, OFFSET_OF(T, reg_init)) );
   __ lwl(t0, MemOperand(a0, OFFSET_OF(T, mem_init)) );
   __ sw(t0, MemOperand(a0, OFFSET_OF(T, lwl_0)) );
 
   __ lw(t1, MemOperand(a0, OFFSET_OF(T, reg_init)) );
   __ lwl(t1, MemOperand(a0, OFFSET_OF(T, mem_init) + 1) );
   __ sw(t1, MemOperand(a0, OFFSET_OF(T, lwl_1)) );
 
@@ skipping 110 matching lines @@
   typedef struct {
       int32_t  x;
       int32_t  y;
       int32_t  y1;
       int32_t  y2;
       int32_t  y3;
       int32_t  y4;
   } T;
   T t;
 
-  MacroAssembler assm(NULL, 0);
+  MacroAssembler assm(Isolate::Current(), NULL, 0);
 
   __ mov(t6, fp);  // Save frame pointer.
   __ mov(fp, a0);  // Access struct T by fp.
   __ lw(t0, MemOperand(a0, OFFSET_OF(T, y)) );
   __ lw(t3, MemOperand(a0, OFFSET_OF(T, y4)) );
 
   __ addu(t1, t0, t3);
   __ subu(t4, t0, t3);
   __ nop();
-  __ Push(t0);  // These instructions disappear after opt.
+  __ push(t0);  // These instructions disappear after opt.
   __ Pop();
   __ addu(t0, t0, t0);
   __ nop();
   __ Pop();     // These instructions disappear after opt.
-  __ Push(t3);
+  __ push(t3);
   __ nop();
-  __ Push(t3);  // These instructions disappear after opt.
-  __ Pop(t3);
+  __ push(t3);  // These instructions disappear after opt.
+  __ pop(t3);
   __ nop();
-  __ Push(t3);
-  __ Pop(t4);
+  __ push(t3);
+  __ pop(t4);
   __ nop();
   __ sw(t0, MemOperand(fp, OFFSET_OF(T, y)) );
   __ lw(t0, MemOperand(fp, OFFSET_OF(T, y)) );
   __ nop();
   __ sw(t0, MemOperand(fp, OFFSET_OF(T, y)) );
   __ lw(t1, MemOperand(fp, OFFSET_OF(T, y)) );
   __ nop();
-  __ Push(t1);
+  __ push(t1);
   __ lw(t1, MemOperand(fp, OFFSET_OF(T, y)) );
-  __ Pop(t1);
+  __ pop(t1);
   __ nop();
-  __ Push(t1);
+  __ push(t1);
   __ lw(t2, MemOperand(fp, OFFSET_OF(T, y)) );
-  __ Pop(t1);
+  __ pop(t1);
   __ nop();
-  __ Push(t1);
+  __ push(t1);
   __ lw(t2, MemOperand(fp, OFFSET_OF(T, y)) );
-  __ Pop(t2);
+  __ pop(t2);
   __ nop();
-  __ Push(t2);
+  __ push(t2);
   __ lw(t2, MemOperand(fp, OFFSET_OF(T, y)) );
-  __ Pop(t1);
+  __ pop(t1);
   __ nop();
-  __ Push(t1);
+  __ push(t1);
   __ lw(t2, MemOperand(fp, OFFSET_OF(T, y)) );
-  __ Pop(t3);
+  __ pop(t3);
   __ nop();
 
   __ mov(fp, t6);
   __ jr(ra);
   __ nop();
 
   CodeDesc desc;
   assm.GetCode(&desc);
   Object* code = HEAP->CreateCode(
       desc,
@@ skipping 23 matching lines @@
   typedef struct {
     double cvt_big_out;
     double cvt_small_out;
     uint32_t trunc_big_out;
     uint32_t trunc_small_out;
     uint32_t cvt_big_in;
     uint32_t cvt_small_in;
   } T;
   T t;
 
-  MacroAssembler assm(NULL, 0);
+  MacroAssembler assm(Isolate::Current(), NULL, 0);
 
-  if (Isolate::Current()->cpu_features()->IsSupported(FPU)) {
+  if (CpuFeatures::IsSupported(FPU)) {
     CpuFeatures::Scope scope(FPU);
 
     __ sw(t0, MemOperand(a0, OFFSET_OF(T, cvt_small_in)));
     __ Cvt_d_uw(f10, t0);
     __ sdc1(f10, MemOperand(a0, OFFSET_OF(T, cvt_small_out)));
 
     __ Trunc_uw_d(f10, f10);
     __ swc1(f10, MemOperand(a0, OFFSET_OF(T, trunc_small_out)));
 
     __ sw(t0, MemOperand(a0, OFFSET_OF(T, cvt_big_in)));
@@ skipping 34 matching lines @@
 TEST(MIPS14) {
   // Test round, floor, ceil, trunc, cvt.
   InitializeVM();
   v8::HandleScope scope;
 
 #define ROUND_STRUCT_ELEMENT(x) \
   int32_t x##_up_out; \
   int32_t x##_down_out; \
   int32_t neg_##x##_up_out; \
   int32_t neg_##x##_down_out; \
-  int32_t x##_err1_out; \
-  int32_t x##_err2_out; \
-  int32_t x##_err3_out; \
-  int32_t x##_err4_out; \
+  uint32_t x##_err1_out; \
+  uint32_t x##_err2_out; \
+  uint32_t x##_err3_out; \
+  uint32_t x##_err4_out; \
   int32_t x##_invalid_result;
 
   typedef struct {
     double round_up_in;
     double round_down_in;
     double neg_round_up_in;
     double neg_round_down_in;
     double err1_in;
     double err2_in;
     double err3_in;
     double err4_in;
 
     ROUND_STRUCT_ELEMENT(round)
     ROUND_STRUCT_ELEMENT(floor)
     ROUND_STRUCT_ELEMENT(ceil)
     ROUND_STRUCT_ELEMENT(trunc)
     ROUND_STRUCT_ELEMENT(cvt)
   } T;
   T t;
 
 #undef ROUND_STRUCT_ELEMENT
 
-  MacroAssembler assm(NULL, 0);
+  MacroAssembler assm(Isolate::Current(), NULL, 0);
 
-  if (Isolate::Current()->cpu_features()->IsSupported(FPU)) {
+  if (CpuFeatures::IsSupported(FPU)) {
     CpuFeatures::Scope scope(FPU);
 
     // Save FCSR.
     __ cfc1(a1, FCSR);
     // Disable FPU exceptions.
     __ ctc1(zero_reg, FCSR);
 #define RUN_ROUND_TEST(x) \
     __ ldc1(f0, MemOperand(a0, OFFSET_OF(T, round_up_in))); \
     __ x##_w_d(f0, f0); \
     __ swc1(f0, MemOperand(a0, OFFSET_OF(T, x##_up_out))); \
@@ skipping 63 matching lines @@
     t.neg_round_up_in = -123.5;
     t.neg_round_down_in = -123.49;
     t.err1_in = 123.51;
     t.err2_in = 1;
     t.err3_in = static_cast<double>(1) + 0xFFFFFFFF;
     t.err4_in = NAN;
 
     Object* dummy = CALL_GENERATED_CODE(f, &t, 0, 0, 0, 0);
     USE(dummy);
 
-#define GET_FPU_ERR(x) ((x >> 2) & (32 - 1))
+#define GET_FPU_ERR(x) (static_cast<int>((x >> kFCSRFlagShift) & kFCSRFlagMask))
 
     CHECK_EQ(124, t.round_up_out);
     CHECK_EQ(123, t.round_down_out);
     CHECK_EQ(-124, t.neg_round_up_out);
     CHECK_EQ(-123, t.neg_round_down_out);
 
-    // Inaccurate.
-    CHECK_EQ(1, GET_FPU_ERR(t.round_err1_out));
+    // Inexact.
+    CHECK_EQ(kFCSRInexactFlagBit, GET_FPU_ERR(t.round_err1_out));
     // No error.
     CHECK_EQ(0, GET_FPU_ERR(t.round_err2_out));
     // Invalid operation.
-    CHECK_EQ(16, GET_FPU_ERR(t.round_err3_out));
-    CHECK_EQ(16, GET_FPU_ERR(t.round_err4_out));
+    CHECK_EQ(kFCSRInvalidOpFlagBit, GET_FPU_ERR(t.round_err3_out));
+    CHECK_EQ(kFCSRInvalidOpFlagBit, GET_FPU_ERR(t.round_err4_out));
     CHECK_EQ(kFPUInvalidResult, t.round_invalid_result);
 
     CHECK_EQ(123, t.floor_up_out);
     CHECK_EQ(123, t.floor_down_out);
     CHECK_EQ(-124, t.neg_floor_up_out);
     CHECK_EQ(-124, t.neg_floor_down_out);
 
-    // Inaccurate.
-    CHECK_EQ(1, GET_FPU_ERR(t.floor_err1_out));
+    // Inexact.
+    CHECK_EQ(kFCSRInexactFlagBit, GET_FPU_ERR(t.floor_err1_out));
     // No error.
     CHECK_EQ(0, GET_FPU_ERR(t.floor_err2_out));
     // Invalid operation.
-    CHECK_EQ(16, GET_FPU_ERR(t.floor_err3_out));
-    CHECK_EQ(16, GET_FPU_ERR(t.floor_err4_out));
+    CHECK_EQ(kFCSRInvalidOpFlagBit, GET_FPU_ERR(t.floor_err3_out));
+    CHECK_EQ(kFCSRInvalidOpFlagBit, GET_FPU_ERR(t.floor_err4_out));
     CHECK_EQ(kFPUInvalidResult, t.floor_invalid_result);
 
     CHECK_EQ(124, t.ceil_up_out);
     CHECK_EQ(124, t.ceil_down_out);
     CHECK_EQ(-123, t.neg_ceil_up_out);
     CHECK_EQ(-123, t.neg_ceil_down_out);
 
-    // Inaccurate.
-    CHECK_EQ(1, GET_FPU_ERR(t.ceil_err1_out));
+    // Inexact.
+    CHECK_EQ(kFCSRInexactFlagBit, GET_FPU_ERR(t.ceil_err1_out));
     // No error.
     CHECK_EQ(0, GET_FPU_ERR(t.ceil_err2_out));
     // Invalid operation.
-    CHECK_EQ(16, GET_FPU_ERR(t.ceil_err3_out));
-    CHECK_EQ(16, GET_FPU_ERR(t.ceil_err4_out));
+    CHECK_EQ(kFCSRInvalidOpFlagBit, GET_FPU_ERR(t.ceil_err3_out));
+    CHECK_EQ(kFCSRInvalidOpFlagBit, GET_FPU_ERR(t.ceil_err4_out));
     CHECK_EQ(kFPUInvalidResult, t.ceil_invalid_result);
 
     // In rounding mode 0 cvt should behave like round.
     CHECK_EQ(t.round_up_out, t.cvt_up_out);
     CHECK_EQ(t.round_down_out, t.cvt_down_out);
     CHECK_EQ(t.neg_round_up_out, t.neg_cvt_up_out);
     CHECK_EQ(t.neg_round_down_out, t.neg_cvt_down_out);
 
-    // Inaccurate.
-    CHECK_EQ(1, GET_FPU_ERR(t.cvt_err1_out));
+    // Inexact.
+    CHECK_EQ(kFCSRInexactFlagBit, GET_FPU_ERR(t.cvt_err1_out));
     // No error.
     CHECK_EQ(0, GET_FPU_ERR(t.cvt_err2_out));
     // Invalid operation.
-    CHECK_EQ(16, GET_FPU_ERR(t.cvt_err3_out));
-    CHECK_EQ(16, GET_FPU_ERR(t.cvt_err4_out));
+    CHECK_EQ(kFCSRInvalidOpFlagBit, GET_FPU_ERR(t.cvt_err3_out));
+    CHECK_EQ(kFCSRInvalidOpFlagBit, GET_FPU_ERR(t.cvt_err4_out));
     CHECK_EQ(kFPUInvalidResult, t.cvt_invalid_result);
   }
 }
 
 
 #undef __