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1 // Copyright 2010 the V8 project authors. All rights reserved. | 1 // Copyright 2010 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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51 // simulate MIPS32 instructions. | 51 // simulate MIPS32 instructions. |
52 // | 52 // |
53 // See: MIPS32 Architecture For Programmers | 53 // See: MIPS32 Architecture For Programmers |
54 // Volume II: The MIPS32 Instruction Set | 54 // Volume II: The MIPS32 Instruction Set |
55 // Try www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf. | 55 // Try www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf. |
56 | 56 |
57 namespace v8 { | 57 namespace v8 { |
58 namespace internal { | 58 namespace internal { |
59 | 59 |
60 // ----------------------------------------------------------------------------- | 60 // ----------------------------------------------------------------------------- |
61 // Registers and FPURegister. | 61 // Registers and FPURegisters. |
62 | 62 |
63 // Number of general purpose registers. | 63 // Number of general purpose registers. |
64 static const int kNumRegisters = 32; | 64 static const int kNumRegisters = 32; |
65 static const int kInvalidRegister = -1; | 65 static const int kInvalidRegister = -1; |
66 | 66 |
67 // Number of registers with HI, LO, and pc. | 67 // Number of registers with HI, LO, and pc. |
68 static const int kNumSimuRegisters = 35; | 68 static const int kNumSimuRegisters = 35; |
69 | 69 |
70 // In the simulator, the PC register is simulated as the 34th register. | 70 // In the simulator, the PC register is simulated as the 34th register. |
71 static const int kPCRegister = 34; | 71 static const int kPCRegister = 34; |
72 | 72 |
73 // Number coprocessor registers. | 73 // Number coprocessor registers. |
74 static const int kNumFPURegisters = 32; | 74 static const int kNumFPURegisters = 32; |
75 static const int kInvalidFPURegister = -1; | 75 static const int kInvalidFPURegister = -1; |
76 | 76 |
77 // FPU (coprocessor 1) control registers. Currently only FCSR is implemented. | 77 // FPU (coprocessor 1) control registers. Currently only FCSR is implemented. |
78 static const int kFCSRRegister = 31; | 78 static const int kFCSRRegister = 31; |
79 static const int kInvalidFPUControlRegister = -1; | 79 static const int kInvalidFPUControlRegister = -1; |
80 static const uint32_t kFPUInvalidResult = (uint32_t) (1 << 31) - 1; | 80 static const uint32_t kFPUInvalidResult = (uint32_t) (1 << 31) - 1; |
81 | 81 |
82 // FCSR constants. | 82 // FCSR constants. |
83 static const uint32_t kFCSRFlagMask = (1 << 6) - 1; | 83 static const uint32_t kFCSRFlagMask = (1 << 6) - 1; |
84 static const uint32_t kFCSRFlagShift = 2; | 84 static const uint32_t kFCSRFlagShift = 2; |
| 85 static const uint32_t kFCSRInexactFlagBit = 1 << 0; |
| 86 static const uint32_t kFCSRUnderflowFlagBit = 1 << 1; |
| 87 static const uint32_t kFCSROverflowFlagBit = 1 << 2; |
| 88 static const uint32_t kFCSRDivideByZeroFlagBit = 1 << 3; |
| 89 static const uint32_t kFCSRInvalidOpFlagBit = 1 << 4; |
85 | 90 |
86 // Helper functions for converting between register numbers and names. | 91 // Helper functions for converting between register numbers and names. |
87 class Registers { | 92 class Registers { |
88 public: | 93 public: |
89 // Return the name of the register. | 94 // Return the name of the register. |
90 static const char* Name(int reg); | 95 static const char* Name(int reg); |
91 | 96 |
92 // Lookup the register number for the name provided. | 97 // Lookup the register number for the name provided. |
93 static int Number(const char* name); | 98 static int Number(const char* name); |
94 | 99 |
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126 static const RegisterAlias aliases_[]; | 131 static const RegisterAlias aliases_[]; |
127 }; | 132 }; |
128 | 133 |
129 | 134 |
130 // ----------------------------------------------------------------------------- | 135 // ----------------------------------------------------------------------------- |
131 // Instructions encoding constants. | 136 // Instructions encoding constants. |
132 | 137 |
133 // On MIPS all instructions are 32 bits. | 138 // On MIPS all instructions are 32 bits. |
134 typedef int32_t Instr; | 139 typedef int32_t Instr; |
135 | 140 |
136 typedef unsigned char byte_; | |
137 | |
138 // Special Software Interrupt codes when used in the presence of the MIPS | 141 // Special Software Interrupt codes when used in the presence of the MIPS |
139 // simulator. | 142 // simulator. |
140 enum SoftwareInterruptCodes { | 143 enum SoftwareInterruptCodes { |
141 // Transition to C code. | 144 // Transition to C code. |
142 call_rt_redirected = 0xfffff | 145 call_rt_redirected = 0xfffff |
143 }; | 146 }; |
144 | 147 |
145 // ----- Fields offset and length. | 148 // ----- Fields offset and length. |
146 static const int kOpcodeShift = 26; | 149 static const int kOpcodeShift = 26; |
147 static const int kOpcodeBits = 6; | 150 static const int kOpcodeBits = 6; |
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168 static const int kFtBits = 5; | 171 static const int kFtBits = 5; |
169 static const int kFdShift = 6; | 172 static const int kFdShift = 6; |
170 static const int kFdBits = 5; | 173 static const int kFdBits = 5; |
171 static const int kFCccShift = 8; | 174 static const int kFCccShift = 8; |
172 static const int kFCccBits = 3; | 175 static const int kFCccBits = 3; |
173 static const int kFBccShift = 18; | 176 static const int kFBccShift = 18; |
174 static const int kFBccBits = 3; | 177 static const int kFBccBits = 3; |
175 static const int kFBtrueShift = 16; | 178 static const int kFBtrueShift = 16; |
176 static const int kFBtrueBits = 1; | 179 static const int kFBtrueBits = 1; |
177 | 180 |
178 // ----- Miscellianous useful masks. | 181 // ----- Miscellaneous useful masks. |
179 // Instruction bit masks. | 182 // Instruction bit masks. |
180 static const int kOpcodeMask = ((1 << kOpcodeBits) - 1) << kOpcodeShift; | 183 static const int kOpcodeMask = ((1 << kOpcodeBits) - 1) << kOpcodeShift; |
181 static const int kImm16Mask = ((1 << kImm16Bits) - 1) << kImm16Shift; | 184 static const int kImm16Mask = ((1 << kImm16Bits) - 1) << kImm16Shift; |
182 static const int kImm26Mask = ((1 << kImm26Bits) - 1) << kImm26Shift; | 185 static const int kImm26Mask = ((1 << kImm26Bits) - 1) << kImm26Shift; |
183 static const int kRsFieldMask = ((1 << kRsBits) - 1) << kRsShift; | 186 static const int kRsFieldMask = ((1 << kRsBits) - 1) << kRsShift; |
184 static const int kRtFieldMask = ((1 << kRtBits) - 1) << kRtShift; | 187 static const int kRtFieldMask = ((1 << kRtBits) - 1) << kRtShift; |
185 static const int kRdFieldMask = ((1 << kRdBits) - 1) << kRdShift; | 188 static const int kRdFieldMask = ((1 << kRdBits) - 1) << kRdShift; |
186 static const int kSaFieldMask = ((1 << kSaBits) - 1) << kSaShift; | 189 static const int kSaFieldMask = ((1 << kSaBits) - 1) << kSaShift; |
187 static const int kFunctionFieldMask = | 190 static const int kFunctionFieldMask = |
188 ((1 << kFunctionBits) - 1) << kFunctionShift; | 191 ((1 << kFunctionBits) - 1) << kFunctionShift; |
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208 | 211 |
209 ADDI = ((1 << 3) + 0) << kOpcodeShift, | 212 ADDI = ((1 << 3) + 0) << kOpcodeShift, |
210 ADDIU = ((1 << 3) + 1) << kOpcodeShift, | 213 ADDIU = ((1 << 3) + 1) << kOpcodeShift, |
211 SLTI = ((1 << 3) + 2) << kOpcodeShift, | 214 SLTI = ((1 << 3) + 2) << kOpcodeShift, |
212 SLTIU = ((1 << 3) + 3) << kOpcodeShift, | 215 SLTIU = ((1 << 3) + 3) << kOpcodeShift, |
213 ANDI = ((1 << 3) + 4) << kOpcodeShift, | 216 ANDI = ((1 << 3) + 4) << kOpcodeShift, |
214 ORI = ((1 << 3) + 5) << kOpcodeShift, | 217 ORI = ((1 << 3) + 5) << kOpcodeShift, |
215 XORI = ((1 << 3) + 6) << kOpcodeShift, | 218 XORI = ((1 << 3) + 6) << kOpcodeShift, |
216 LUI = ((1 << 3) + 7) << kOpcodeShift, | 219 LUI = ((1 << 3) + 7) << kOpcodeShift, |
217 | 220 |
218 COP1 = ((2 << 3) + 1) << kOpcodeShift, // Coprocessor 1 class | 221 COP1 = ((2 << 3) + 1) << kOpcodeShift, // Coprocessor 1 class. |
219 BEQL = ((2 << 3) + 4) << kOpcodeShift, | 222 BEQL = ((2 << 3) + 4) << kOpcodeShift, |
220 BNEL = ((2 << 3) + 5) << kOpcodeShift, | 223 BNEL = ((2 << 3) + 5) << kOpcodeShift, |
221 BLEZL = ((2 << 3) + 6) << kOpcodeShift, | 224 BLEZL = ((2 << 3) + 6) << kOpcodeShift, |
222 BGTZL = ((2 << 3) + 7) << kOpcodeShift, | 225 BGTZL = ((2 << 3) + 7) << kOpcodeShift, |
223 | 226 |
224 SPECIAL2 = ((3 << 3) + 4) << kOpcodeShift, | 227 SPECIAL2 = ((3 << 3) + 4) << kOpcodeShift, |
225 SPECIAL3 = ((3 << 3) + 7) << kOpcodeShift, | 228 SPECIAL3 = ((3 << 3) + 7) << kOpcodeShift, |
226 | 229 |
227 LB = ((4 << 3) + 0) << kOpcodeShift, | 230 LB = ((4 << 3) + 0) << kOpcodeShift, |
228 LH = ((4 << 3) + 1) << kOpcodeShift, | 231 LH = ((4 << 3) + 1) << kOpcodeShift, |
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386 positive = 9, | 389 positive = 9, |
387 parity_even = 10, | 390 parity_even = 10, |
388 parity_odd = 11, | 391 parity_odd = 11, |
389 less = 12, | 392 less = 12, |
390 greater_equal = 13, | 393 greater_equal = 13, |
391 less_equal = 14, | 394 less_equal = 14, |
392 greater = 15, | 395 greater = 15, |
393 | 396 |
394 cc_always = 16, | 397 cc_always = 16, |
395 | 398 |
396 // aliases | 399 // Aliases. |
397 carry = Uless, | 400 carry = Uless, |
398 not_carry = Ugreater_equal, | 401 not_carry = Ugreater_equal, |
399 zero = equal, | 402 zero = equal, |
400 eq = equal, | 403 eq = equal, |
401 not_zero = not_equal, | 404 not_zero = not_equal, |
402 ne = not_equal, | 405 ne = not_equal, |
403 nz = not_equal, | 406 nz = not_equal, |
404 sign = negative, | 407 sign = negative, |
405 not_sign = positive, | 408 not_sign = positive, |
406 mi = negative, | 409 mi = negative, |
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448 case less_equal: | 451 case less_equal: |
449 return greater_equal; | 452 return greater_equal; |
450 default: | 453 default: |
451 return cc; | 454 return cc; |
452 }; | 455 }; |
453 } | 456 } |
454 | 457 |
455 | 458 |
456 // ----- Coprocessor conditions. | 459 // ----- Coprocessor conditions. |
457 enum FPUCondition { | 460 enum FPUCondition { |
458 F, // False | 461 F, // False. |
459 UN, // Unordered | 462 UN, // Unordered. |
460 EQ, // Equal | 463 EQ, // Equal. |
461 UEQ, // Unordered or Equal | 464 UEQ, // Unordered or Equal. |
462 OLT, // Ordered or Less Than | 465 OLT, // Ordered or Less Than. |
463 ULT, // Unordered or Less Than | 466 ULT, // Unordered or Less Than. |
464 OLE, // Ordered or Less Than or Equal | 467 OLE, // Ordered or Less Than or Equal. |
465 ULE // Unordered or Less Than or Equal | 468 ULE // Unordered or Less Than or Equal. |
466 }; | 469 }; |
467 | 470 |
468 | 471 |
469 // ----------------------------------------------------------------------------- | 472 // ----------------------------------------------------------------------------- |
470 // Hints. | 473 // Hints. |
471 | 474 |
472 // Branch hints are not used on the MIPS. They are defined so that they can | 475 // Branch hints are not used on the MIPS. They are defined so that they can |
473 // appear in shared function signatures, but will be ignored in MIPS | 476 // appear in shared function signatures, but will be ignored in MIPS |
474 // implementations. | 477 // implementations. |
475 enum Hint { | 478 enum Hint { |
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487 // These constants are declared in assembler-mips.cc, as they use named | 490 // These constants are declared in assembler-mips.cc, as they use named |
488 // registers and other constants. | 491 // registers and other constants. |
489 | 492 |
490 // addiu(sp, sp, 4) aka Pop() operation or part of Pop(r) | 493 // addiu(sp, sp, 4) aka Pop() operation or part of Pop(r) |
491 // operations as post-increment of sp. | 494 // operations as post-increment of sp. |
492 extern const Instr kPopInstruction; | 495 extern const Instr kPopInstruction; |
493 // addiu(sp, sp, -4) part of Push(r) operation as pre-decrement of sp. | 496 // addiu(sp, sp, -4) part of Push(r) operation as pre-decrement of sp. |
494 extern const Instr kPushInstruction; | 497 extern const Instr kPushInstruction; |
495 // sw(r, MemOperand(sp, 0)) | 498 // sw(r, MemOperand(sp, 0)) |
496 extern const Instr kPushRegPattern; | 499 extern const Instr kPushRegPattern; |
497 // lw(r, MemOperand(sp, 0)) | 500 // lw(r, MemOperand(sp, 0)) |
498 extern const Instr kPopRegPattern; | 501 extern const Instr kPopRegPattern; |
499 extern const Instr kLwRegFpOffsetPattern; | 502 extern const Instr kLwRegFpOffsetPattern; |
500 extern const Instr kSwRegFpOffsetPattern; | 503 extern const Instr kSwRegFpOffsetPattern; |
501 extern const Instr kLwRegFpNegOffsetPattern; | 504 extern const Instr kLwRegFpNegOffsetPattern; |
502 extern const Instr kSwRegFpNegOffsetPattern; | 505 extern const Instr kSwRegFpNegOffsetPattern; |
503 // A mask for the Rt register for push, pop, lw, sw instructions. | 506 // A mask for the Rt register for push, pop, lw, sw instructions. |
504 extern const Instr kRtMask; | 507 extern const Instr kRtMask; |
505 extern const Instr kLwSwInstrTypeMask; | 508 extern const Instr kLwSwInstrTypeMask; |
506 extern const Instr kLwSwInstrArgumentMask; | 509 extern const Instr kLwSwInstrArgumentMask; |
507 extern const Instr kLwSwOffsetMask; | 510 extern const Instr kLwSwOffsetMask; |
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680 bool IsForbiddenInBranchDelay() const; | 683 bool IsForbiddenInBranchDelay() const; |
681 // Say if the instruction 'links'. eg: jal, bal. | 684 // Say if the instruction 'links'. eg: jal, bal. |
682 bool IsLinkingInstruction() const; | 685 bool IsLinkingInstruction() const; |
683 // Say if the instruction is a break or a trap. | 686 // Say if the instruction is a break or a trap. |
684 bool IsTrap() const; | 687 bool IsTrap() const; |
685 | 688 |
686 // Instructions are read of out a code stream. The only way to get a | 689 // Instructions are read of out a code stream. The only way to get a |
687 // reference to an instruction is to convert a pointer. There is no way | 690 // reference to an instruction is to convert a pointer. There is no way |
688 // to allocate or create instances of class Instruction. | 691 // to allocate or create instances of class Instruction. |
689 // Use the At(pc) function to create references to Instruction. | 692 // Use the At(pc) function to create references to Instruction. |
690 static Instruction* At(byte_* pc) { | 693 static Instruction* At(byte* pc) { |
691 return reinterpret_cast<Instruction*>(pc); | 694 return reinterpret_cast<Instruction*>(pc); |
692 } | 695 } |
693 | 696 |
694 private: | 697 private: |
695 // We need to prevent the creation of instances of class Instruction. | 698 // We need to prevent the creation of instances of class Instruction. |
696 DISALLOW_IMPLICIT_CONSTRUCTORS(Instruction); | 699 DISALLOW_IMPLICIT_CONSTRUCTORS(Instruction); |
697 }; | 700 }; |
698 | 701 |
699 | 702 |
700 // ----------------------------------------------------------------------------- | 703 // ----------------------------------------------------------------------------- |
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714 | 717 |
715 static const int kDoubleAlignmentBits = 3; | 718 static const int kDoubleAlignmentBits = 3; |
716 static const int kDoubleAlignment = (1 << kDoubleAlignmentBits); | 719 static const int kDoubleAlignment = (1 << kDoubleAlignmentBits); |
717 static const int kDoubleAlignmentMask = kDoubleAlignment - 1; | 720 static const int kDoubleAlignmentMask = kDoubleAlignment - 1; |
718 | 721 |
719 | 722 |
720 } } // namespace v8::internal | 723 } } // namespace v8::internal |
721 | 724 |
722 #endif // #ifndef V8_MIPS_CONSTANTS_H_ | 725 #endif // #ifndef V8_MIPS_CONSTANTS_H_ |
723 | 726 |
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