Update mips infrastructure files.

src/mips/constants-mips.cc

-// Copyright 2010 the V8 project authors. All rights reserved.
+// Copyright 2011 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
 //       with the distribution.
@@ skipping 17 matching lines @@
 
 #if defined(V8_TARGET_ARCH_MIPS)
 
 #include "constants-mips.h"
 
 namespace v8 {
 namespace internal {
 
 
 // -----------------------------------------------------------------------------
-// Registers
+// Registers.
 
 
 // These register names are defined in a way to match the native disassembler
 // formatting. See for example the command "objdump -d <binary file>".
 const char* Registers::names_[kNumSimuRegisters] = {
   "zero_reg",
   "at",
   "v0", "v1",
   "a0", "a1", "a2", "a3",
   "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
@@ skipping 88 matching lines @@
     }
     i++;
   }
 
   // No Cregister with the reguested name found.
   return kInvalidFPURegister;
 }
 
 
 // -----------------------------------------------------------------------------
-// Instruction
+// Instructions.
 
 bool Instruction::IsForbiddenInBranchDelay() const {
   const int op = OpcodeFieldRaw();
   switch (op) {
     case J:
     case JAL:
     case BEQ:
     case BNE:
     case BLEZ:
     case BGTZ:
@@ skipping 127 matching lines @@
       break;
     case SPECIAL3:
       switch (FunctionFieldRaw()) {
         case INS:
         case EXT:
           return kRegisterType;
         default:
           UNREACHABLE();
       };
       break;
-    case COP1:    // Coprocessor instructions
+    case COP1:    // Coprocessor instructions.
       switch (RsFieldRawNoAssert()) {
-        case BC1:   // branch on coprocessor condition
+        case BC1:   // Branch on coprocessor condition.
           return kImmediateType;
         default:
           return kRegisterType;
       };
       break;
-    // 16 bits Immediate type instructions. eg: addi dest, src, imm16
+    // 16 bits Immediate type instructions. eg: addi dest, src, imm16.
     case REGIMM:
     case BEQ:
     case BNE:
     case BLEZ:
     case BGTZ:
     case ADDI:
     case ADDIU:
     case SLTI:
     case SLTIU:
     case ANDI:
@@ skipping 14 matching lines @@
     case SB:
     case SH:
     case SWL:
     case SW:
     case SWR:
     case LWC1:
     case LDC1:
     case SWC1:
     case SDC1:
       return kImmediateType;
-    // 26 bits immediate type instructions. eg: j imm26
+    // 26 bits immediate type instructions. eg: j imm26.
     case J:
     case JAL:
       return kJumpType;
     default:
       UNREACHABLE();
   };
   return kUnsupported;
 }
 
 
 } }   // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_MIPS